TMS320TCI6486 Datasheet, PDF (184/268 Pages) Texas Instruments – TMS320TCI6486 Communications Infrastructure Digital Signal Processor

TMS320TCI6486
SPRS300N – FEBRUARY 2006 – REVISED JULY 2011
www.ti.com
7.13.4 HPI Electrical Data/Timing
Table 7-54. Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾
(see Figure 7-41 through Figure 7-44)
500/625/700
NO.
UNIT
MIN
MAX
9
t_{su(HASL-HSTBL)}
Setup time, HAS low before HSTROBE low
5
ns
10
t_{h(HSTBL-HASL)}
11
t_{su(SELV-HASL)}
12
t_h(HASL-SELV)
Hold time, HAS low after HSTROBE low
Setup time, select signals⁽³⁾ valid before HAS low
Hold time, select signals⁽³⁾ valid after HAS low
2
ns
5
ns
5
ns
13
t_w(HSTBL)
Pulse duration, HSTROBE low
2M
ns
14
t_w(HSTBH)
15
t_{su(SELV-HSTBL)}
16
t_{h(HSTBL-SELV)}
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
2M
ns
5
ns
5
ns
17
t_{su(HDV-HSTBH)}
Setup time, host data valid before HSTROBE high
6
ns
18
t_h(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
0
ns
37
t_{su(HCSL-HSTBL)}
Setup time, HCS low before HSTROBE low
0
ns
38
t_{h(HRDYL-HSTBL)}
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
0
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) M = HPI module clock period = 6 * CPU clock period or 12 ns at 500 MHz. (This duration will be much longer when PLL1 is in bypass
mode.)
(3) Select signals (SELV) include: HCNTL[1:0] and HR/W and HHWIL.
184 C64x+ Peripheral Information and Electrical Specifications
Copyright © 2006–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s) :TMS320TCI6486