TMS320TCI6486 Datasheet, PDF (15/268 Pages) Texas Instruments – TMS320TCI6486 Communications Infrastructure Digital Signal Processor

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TMS320TCI6486
SPRS300N – FEBRUARY 2006 – REVISED JULY 2011
Table 2-3. Boot Mode Operation
BOOTMODE[3:0]
0 (0000)
1 (0001)
DESCRIPTION
Immediate boot
Host boot (HPI)
2 (0010)
Master I2C boot for I2C address 50h
3 (0011)
Master I2C boot for I2C address 51h
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
Slave I2C boot
UTOPIA boot 8-bit PLLx10 of main
PLLCTL
UTOPIA boot 8-bit PLLx20 of main
PLLCTL
UTOPIA boot 16-bit PLLx10 of main
PLLCTL
UTOPIA boot 16-bit PLLx20 of main
PLLCTL
Ethernet MAC Port 0 boot
(mode and speed determined by
MACSEL0 pins)
10 (1010)
Ethernet MAC Port 1 boot
(mode and speed determined by
MACSEL1 pins)
11 (1011)
RIO1
12 (1100)
RIO2
TYPE
Immediate Boot
Host
ROM
ROM
ROM
ROM
CFGGP[4:0]
Don’t Care
Don’t Care
CFGGP[4] =
0
PLLx9 mode of main PLLCTL is selected
1
PLLx19 mode of main PLLCTL is
selected
CFGGP[3:0] = Boot PARAM index
CFGGP[4] =
0
PLLx9 mode of main PLLCTL is selected
1
PLLx19 mode of main PLLCTL is
selected
CFGGP[3:0] = Boot PARAM index
CFGGP[4] =
0
PLLx9 mode of main PLLCTL is selected
1
PLLx19 mode of main PLLCTL is
selected
CFGGP[3:0] = Don’t Care
PHY ID
ROM
PHY ID
ROM
PHY ID
ROM
PHY ID
ROM
ROM
ROM
ROM
CFGGP[4] =
0
PLLx10 mode of main PLLCTL is
selected
1
PLLx20 mode of main PLLCTL is
selected
CFGGP[3:0]: Device ID (when RMII is selected,
CFGGP[3] controls speed - 1 for 100 Mbs, 0 for 10
Mbps - and Device ID[3] is 0)
CFGGP[4] =
0
PLLx10 mode of main PLLCTL is
selected
1
PLLx20 mode of main PLLCTL is
selected
CFGGP[3:0]: Device ID (when RMII is selected,
CFGGP[3] controls speed - 1 for 100 Mbs, 0 for 10
Mbps - and Device ID[3] is 0)
CFGGP[4] =
0
PLLx10 mode of main PLLCTL is
selected
1
PLLx20 mode of main PLLCTL is
selected
CFGGP [3:0]: Node (1111b for default)
CFGGP[4] =
0
PLLx10 mode of main PLLCTL is
selected
1
PLLx20 mode of main PLLCTL is
selected
CFGGP [3:0]: Node (1111b for default)
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