LP3954 Datasheet, PDF (34/60 Pages) National Semiconductor (TI) – Advanced Lighting Management Unit

LP3954
SNVS340D – JUNE 2005 – REVISED MARCH 2013
Symbol
3
4
5
6
7
8
9
10
11
Enable Lag Time
Clock Low Time
Clock High Time
Data Setup Time
Data Hold Time
Data Access Time
Disable Time
Data Valid
Data Hold Time
Parameter
Limit ⁽¹⁾
Min
Max
35
35
35
20
0
20
10
20
0
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
I²C COMPATIBLE INTERFACE
I²C Signals
In I²C mode the LP3954 pin SCK is used for the I²C clock SCL and the pin SS is used for the I²C data signal
SDA. Both these signals need a pull-up resistor according to I²C specification. SI pin is the address select pin.
I²C address for LP3954 is 54h when SI = 0 and 55h when SI = 1. Unused pin SO can be left unconnected.
I²C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 38. I²C Signals: Data Validity
I²C Start and Stop Conditions
START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits.
The I²C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I²C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
START condition
P
STOP condition
34
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