LP3954 Datasheet, PDF (33/60 Pages) National Semiconductor (TI) – Advanced Lighting Management Unit

LP3954
www.ti.com
SNVS340D – JUNE 2005 – REVISED MARCH 2013
SPI INTERFACE
LP3954 is compatible with SPI serial bus specification and it operates as a slave. The transmission consists of
16-bit Write and Read Cycles. One cycle consists of 7 Address bits, 1 Read/Write (RW) bit and 8 Data bits. RW
bit high state defines a Write Cycle and low defines a Read Cycle. SO output is normally in high-impedance state
and it is active only when Data is sent out during a Read Cycle. A pull-up resistor may be needed in SO line if a
floating logic signal can cause unintended current consumption in the input circuits where SO is connected.The
Address and Data are transmitted MSB first. The Slave Select signal SS must be low during the Cycle
transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is
clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK.
SS
SCK
SI
A6 A5 A4 A3 A2 A1 A0 ¹ D7 D6 D5 D4 D3 D2 D1 D0
R/W
SO
Figure 35. SPI Write Cycle
SS
SCK
SI
SO
R/W
A6 A5 A4 A3 A2 A1 A0 ₀
Don't Care
D7 D6 D5 D4 D3 D2 D1 D0
Figure 36. SPI Read Cycle
SS
SCK
SI
SO
2
1
5
4
7
6
MSB IN
BIT 14
BIT 9
BIT 8
BIT 7
8
10
MSB OUT
Address
R/W
Figure 37. SPI Timing Diagram
SPI Timing Parameters
V_DD = V_{DD_IO} = 2.775V
Symbol
1
2
Cycle Time
Enable Lead Time
Parameter
(1) Note: Data ensured by design.
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LP3954
3
12
BIT 1 LSB IN
BIT 1
11
9
LSB OUT
Data
Limit ⁽¹⁾
Min
Max
70
35
Unit
ns
ns
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