CC2550_13 Datasheet, PDF (34/61 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transmitter

CC2550
reset, this can be used to clock the MCU in
systems with only one crystal. When the MCU
is up and running, it can change the clock
frequency by writing to IOCFG0.GDO0_CFG.
An on-chip analog temperature sensor is
enabled by writing the value 128 (0x80) to the
IOCFG0.GDO0_CFG register. The voltage on
the GDO0 pin is then proportional to
temperature. See Section 4.5 on page 8 for
temperature sensor specifications.
In SLEEP mode, GDO1 will be hardwired to 1
and GDO0 will be high impedance.
GDOx_CFG[5:0] Description
0 (0x00) Reserved – defined in the transceiver version.
1 (0x01) Reserved – defined in the transceiver version.
2 (0x02)
Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the
TX FIFO is below the same threshold.
3 (0x03)
Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO
threshold.
4 (0x04) Reserved – defined in the transceiver version.
5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
6 (0x06)
Asserts when sync word has been sent, and de-asserts at the end of the packet. The pin will also de-assert if the TX
FIFO underflows.
7 (0x07)
to
Reserved
9 (0x09)
10 (0x0A)
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To
check for PLL lock the lock detector output should be used as an interrupt for the MCU.
11 (0x0B)
Serial Clock. Synchronous to the data in synchronous serial mode.
In TX mode, data is sampled by CC2550 on the rising edge of the serial clock when GDOx_INV=0.
12 (0x0C)
to
Reserved – used for test.
40 (0x28)
41 (0x29) CHIP_RDY
42 (0x2A) Reserved – used for test.
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test.
45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved with _INV signal). Can be used to control an external PA
48 (0x30) CLK_XOSC/1
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4
53 (0x35) CLK_XOSC/6
54 (0x36)
55 (0x37)
56 (0x38)
57 (0x39)
CLK_XOSC/8
CLK_XOSC/12
CLK_XOSC/16
CLK_XOSC/24
Note: There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any
time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other GDO pin must be
configured to a value less than 0x30. The GDO0 default value is CLK_XOSC/192.
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192
Table 22: GDOx Signal Selection (x = 0 or 1)
26 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have
been included in the CC2550 to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller and
simplify software development.
26.1 Asynchronous Operation
For backward compatibility with systems
already using the asynchronous data transfer
from other Chipcon products, asynchronous
SWRS039B
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