CC2550_13 Datasheet, PDF (33/61 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transmitter

CC2550
24 PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be filled
with metallization connected to ground using
several vias.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias for good thermal
performance and sufficiently low inductance to
ground. In the CC2550EM reference designs
[3] 5 vias are placed inside the exposed die
attached pad. These vias should be “tented”
(covered with solder mask) on the component
side of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%.
See Figure 21 for top solder resist and top
paste masks. See Figure 24 for recommended
PCB layout for QLP 16 package.
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed to decouple. Each decoupling
capacitor should be connected to the power
line by separate vias. The best routing is from
the power line to the decoupling capacitor and
then to the CC2550 supply pin. Supply power
filtering is very important.
Each decoupling capacitor ground pad should
be connected to the ground plane using a
separate via. Direct connections between
neighboring power pins will increase noise
coupling and should be avoided unless
absolutely necessary.
The external components should ideally be as
small as possible (0402 is recommended) and
surface mount devices are highly
recommended. Please note that components
smaller than those specified may have
differing characteristics.
Precaution should be used when placing the
microcontroller in order to avoid noise
interfering with the RF circuitry.
A CC2500/2550DK Development Kit with a
fully assembled CC2550EM Evaluation
Module is available. It is strongly advised that
this reference layout is followed very closely in
order to get the best performance. The
schematic, BOM and layout Gerber files are all
available from the TI website [3].
Figure 21: Left: Top Paste Mask. Right: Top Solder Resist Mask (negative). Circles are Vias.
25 General Purpose / Test Output Control Pins
The two digital output pins GDO0 and GDO1 are
general control pins configured with
IOCFG0.GDO0_CFG
and
IOCFG1.GDO1_CFG respectively. Table 22
shows the different signals that can be
monitored on the GDO pins. These signals can
be used as inputs to the MCU. GDO1 is the
same pin as the SO pin on the SPI interface,
thus the output programmed on this pin will
only be valid when CSn is high. The default
value for GDO1 is 3-stated, which is useful
when the SPI interface is shared with other
devices.
The default value for GDO0 is a 135-141 kHz
clock output (XOSC frequency divided by 192).
Since the XOSC is turned on at power-on-
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