CC2550_13 Datasheet, PDF (15/61 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transmitter

CC2550
t _sp
t _ch
t_cl
t _sd
t_hd
t_ns
SCLK:
CSn:
Write to register:
SI ^{X 0}
B
A5
A4
A3
A2
A1
A0 X DW 7 DW6 DW5 DW4 DW3 DW2 DW 1 DW 0
S O ^{Hi-Z S7}
B
S5 S4 S3
S2 S1 S0
S7
S6
S5 S4 S3 S2 S1 S0
Read from register:
X
Hi- Z
SI ^{X 1}
B A5 A4 A3 A2 A1 A0
X
S O ^{Hi-Z S7}
B
S5 S4 S3 S2 S1 S0
DR7
DR 6 DR 5 DR 4 DR 3 DR 2 DR 1
DR0
Hi- Z
Figure 6: Configuration Registers Write and Read Operations
Parameter Description
Min
f_SCLK
SCLK frequency
-
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
SCLK frequency, single access
No delay between address and data byte
SCLK frequency, burst access
No delay between address and data byte, or between data bytes
t_sp,pd
CSn low to positive edge on SCLK, in power-down mode
150
t_sp
CSn low to positive edge on SCLK, in active mode
20
t_ch
Clock high
50
t_cl
Clock low
50
t_rise
Clock rise time
-
t_fall
Clock fall time
-
t_sd
Setup data (negative SCLK edge) to
Single access
55
positive edge on SCLK
(t_sd applies between address and data bytes, and
Burst access
76
between data bytes)
t_hd
Hold data after positive edge on SCLK
20
t_ns
Negative edge on SCLK to CSn high
20
Max
Units
10
MHz
9
MHz
6.5
MHz
-
µs
-
ns
-
ns
-
ns
5
ns
5
ns
-
ns
-
ns
-
ns
-
ns
Table 14: SPI Interface Timing Requirements
Note: The minimum t_sp,pd figure in Table 14 can be used in cases where the user does not read the
CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down
depends on the start-up time of the crystal being used. The 150 us in Table 14 is the crystal oscillator
start-up time measured on CC2550EM reference design ([3]) using crystal AT-41CD2 from NDK.
10.1 Chip Status Byte
When the header byte, data byte, or command
strobe is sent on the SPI interface, the chip
status byte is sent by the CC2550 on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
the CHIP_RDYn signal; this signal must go low
before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is
running.
Bits 6, 5, and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core is on in the
IDLE state, but all other modules are in power
SWRS039B
Page 15 of 58