CC2550_13 Datasheet, PDF (17/61 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transmitter

CC2550
by the radio hardware (e.g. MARCSTATE or
TXBYTES), there is a small, but finite,
probability that a single read from the register
is being corrupt. As an example, the probability
of any single read from TXBYTES being
corrupt, assuming the maximum data rate is
used, is approximately 80 ppm. Refer to the
CC2550 Errata Note [1] for more details.
one header byte and then consecutive data
bytes until terminating the access by setting
CSn high.
The following header bytes access the FIFO:
• 0x3F: Single byte access to TX FIFO
• 0x7F: Burst access to TX FIFO
10.4 Command Strobes
Command strobes may be viewed as single
byte instructions to CC2550. By addressing a
command strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable transmit
mode, flush the TX FIFO etc. The 9 command
strobes are listed in Table 23 on page 38.
The command strobe registers are accessed
by transferring a single header byte (no data is
being transferred). That is, only the R/W bit,
the burst access bit (set to 0), and the six
address bits (in the range 0x30 through 0x3D)
are written.
When writing command strobes, the status
byte is sent on the SO pin.
A command strobe may be followed by any
other SPI access without pulling CSn high.
However, if an SRES strobe is being issued,
one will have to wait for SO to go low again
before the next header byte can be issued as
shown in Figure 7. The command strobes are
executed immediately, with the exception of
the SPWD and the SXOFF strobes that are
executed when CSn goes high.
Figure 7: SRES Command Strobe
10.5 FIFO Access
The 64-byte TX FIFO is accessed through the
0x3F address and is write-only.
The burst bit is used to determine if the FIFO
access is a single byte access or a burst
access. The single byte access method
expects a header byte with the burst bit set to
zero and one data byte. After the data byte a
new header byte is expected; hence, CSn can
remain low. The burst access method expects
When writing to the TX FIFO, the status byte
(see Section 10.1) is output for each new data
byte on SO, as shown in Figure 6. This status
byte can be used to detect TX FIFO underflow
while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
free before writing the byte in progress to the
TX FIFO. When the last byte that fits in the TX
FIFO is transmitted on SI, the status byte
received concurrently on SO will indicate that
one byte is free in the TX FIFO.
The TX FIFO may be flushed by issuing a
SFTX command strobe. A SFTX command
strobe can only be issued in the IDLE or
TX_UNDERFLOW states. The TX FIFO is
flushed when going to the SLEEP state.
Figure 8 gives a brief overview of different
register access types possible.
10.6 PATABLE Access
The 0x3E address is used to access the
PATABLE, which is used for selecting PA
power control settings. The PATABLE is an 8-
byte table, but not all entries into this table are
used. The entries to use are selected by the 3-
bit value FREND0.PA_POWER.
• When using 2-FSK, GFSK, or MSK
modulation only the first entry into this
table is used (index 0).
• When using OOK modulation the first two
entries into this table are used (index 0
and index 1).
Since the PATABLE is an 8-byte table, the
table is written and read from the lowest
setting (0) to the highest (7), one byte at a
time. An index counter is used to control the
access to the table. This counter is
incremented each time a byte is read or written
to the table, and set to the lowest index when
CSn is high. When the highest value is
reached the counter restarts at 0.
SWRS039B
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