BQ25703A Datasheet, PDF (34/81 Pages) Texas Instruments – I2C Multi-Chemistry Battery Buck-Boost Charge Controller With System Power Monitor and Processor Hot Monitor

bq25703A
SLUSCU1 – MAY 2017
8.6.1 Setting Charge and PROCHOT Options
8.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E20Eh]
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Figure 23. ChargeOption0 Register (I2C address = 01h/00h) [reset = E20Eh]
15
EN_LWPWR
R/W
14
13
WDTMR_ADJ
R/W
12
IDPM_AUTO_
DISABLE
R/W
11
OTG_ON_
CHRGOK
R/W
10
EN_OOA
R/W
9
PWM_FREQ
R/W
8
Reserved
R/W
7
6
5
4
Reserved
EN_LEARN IADPT_GAIN
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
IBAT_GAIN
R/W
2
EN_LDO
R/W
1
EN_IDPM
R/W
0
CHRG_INHIBIT
R/W
Table 5. ChargeOption0 Register (I2C address = 01h) Field Descriptions
I2C
01h
FIELD
7 EN_LWPWR
6-5 WDTMR_ADJ
4 IDPM_AUTO_
DISABLE
3 OTG_ON_
CHRGOK
2 EN_OOA
TYPE
R/W
R/W
R/W
R/W
R/W
RESET
1b
11b
0b
0b
0b
DESCRIPTION
Low Power Mode Enable
0b: Disable Low Power Mode. Device in performance mode with battery only.
The PROCHOT, current/power monitor buffer and comparator follow register
setting.
1b: Enable Low Power Mode. Device in low power mode with battery only for
lowest quiescent current. PROCHOT, discharge current monitor buffer, power
monitor buffer and independent comparator are disabled. ADC is not available
in Low Power Mode.Independent comparator can be enabled by setting either
REG0X31()[6] or [5] to 1. <default at POR>
WATCHDOG Timer Adjust
Set maximum delay between consecutive I2C write of charge voltage or charge
current command.
If device does not receive a write on the REG0x05/04() or the REG0x03/02()
within the watchdog time period, the charger will be suspended by setting the
REG0x03/02() to 0 mA.
After expiration, the timer will resume upon the write of REG0x03/02(),
REG0x05/04() or REG0x01[6:5]. The charger will resume if the values are
valid.
00b: Disable Watchdog Timer
01b: Enabled, 5 sec
10b: Enabled, 88 sec
11b: Enable Watchdog Timer, 175 sec <default at POR>
IDPM Auto Disable
When CELL_BATPRESZ pin is LOW, the charger automatically disables the
IDPM function by setting EN_IDPM (REG0x00[1]) to 0. The host can enable
IDPM function later by writing EN_IDPM bit (REG0x00[1]) to 1.
0b: Disable this function. IDPM is not disabled when CELL_BATPRESZ goes
LOW. <default at POR>
1b: Enable this function. IDPM is disabled when CELL_BATPRESZ goes LOW.
Add OTG to CHRG_OK
Drive CHRG_OK to HIGH when the device is in OTG mode.
0b: Disable <default at POR>
1b: Enable
Out-of-Audio Enable
0b: No limit of PFM burst frequency <default at POR>
1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise
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