BQ25703A Datasheet, PDF (29/81 Pages) Texas Instruments – I2C Multi-Chemistry Battery Buck-Boost Charge Controller With System Power Monitor and Processor Hot Monitor

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bq25703A
SLUSCU1 – MAY 2017
8.5 Programming
The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in . The SMBUS address is 12h (0001001_X), where X is the read/write bit. The ManufacturerID and
DeviceID registers are assigned identify the charger device. The ManufacturerID register command always
returns 40h.
8.5.1 I²C Serial Interface
The bq25703A uses I2C compatible interface for flexible charging parameter programming and instantaneous
device status reporting. I²C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data
line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data
transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address D6h, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG0F. The I²C interface supports both standard
mode (up to 100 kbits), and fast mode (up to 400 kbits). connecting to the positive supply voltage via a current
source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
8.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
Figure 15. Bit Transfer on the I²C Bus
8.5.1.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
START (S)
STOP (P)
Figure 16. START and STOP Conditions
Copyright © 2017, Texas Instruments Incorporated
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