TLC59291_16 Datasheet, PDF (31/46 Pages) Texas Instruments – 8/16-Channel, Constant Current LED Driver

www.ti.com
LOD
LED is not opened
(V_OUTn > V_LOD)
LED is open or shorted to GND
(V_OUTn ≤ V_LOD)
TLC59291
SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
Table 5. LOD/LSD/OLD Truth Table
LSD
LED is not shorted (V_OUTn ≤ V_LSD)
LED is shorted between anode and
cathode, or shorted to higher voltage
side (V_OUTn > V_LSD)
OLD
OUTn does not leak to GND (V_OUTn >
V_LSD when constant-current output off
and OUTn source current on)
Current leaks from OUTn to internal
GND, or OUTn is shorted to external
GND with high impedance (V_OUTn ≤
V_LSD when constant-current output off
and OUTn source current on)
CORRESPONDING BIT IN SID
0
1
8.5 Register Maps
8.5.1 Register and Data Latch Configuration
The TLC59291 has one common shift register and two control data latch. The common shift register is 16-bits in
length and two control data latch is 16-bits length. When SCLK is '0' at LAT rising edge, the 16-bits common shift
register are copied into the output on-off data latch. Also when SCLK is '1' at LAT rising edge the 16-bits data are
copied into the control data latch. Figure 31 shows the common shift register and two control data latches
configuration.
SOUT
Common shift register (16 bits)
SID 16 bit
MSB
Common
Data bit
15
Common Common
Data bit Data bit
14
13
Common
Data bit
12
Common
Data bit
11
15
14
13
12
11
---
LSB
Common Common Common Common Common
Data bit Data bit Data bit Data bit Data bit
4
3
2
1
0
4
3
2
1
0
SIN
SCLK
16 bit
Output on - off data latch (16 bits)
MSB
15
14
13
12
11
OUTON OUTON OUTON OUTON OUTON
15
14
13
12
11
LSB
---
4
3
2
1
0
The latch pulse
OUTON OUTON OUTON OUTON OUTON
4
3
2
1
0
comes from LAT
pin when SCLK
signal = 0.
0
16 bit
To output on-off control circuit
Control data latch (16 bits)
16 bit
MSB
15
14
13
12
11
10
9
8
7
6
---
Power
save
enable
IDM
IDM
working working
time 1 time 0
IDM
current
select 1
IDM
LSD
LSD _{SID load} SID load Brightness
current detect detect control control control
select 0 voltage1 voltage0
1
0
(BC) 6
LSB
0
Brightness
control
(BC) 0
The latch pulse
comes from LAT
pin when SCLK
signal = 1.
1 bit
2 bit
2 bit
2 bit
2 bit
7 bit
To power
save mode
control
circuit
To IDM
working time
control
circuit
To IDM
current
control
circuit
To LSD
circuit
To SID
data load
control
circuit
To output constant current
control circuit
Figure 31. Common Shift Register and Control Data Latches Configuration
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TLC59291
Submit Documentation Feedback
31