TLC59291_16 Datasheet, PDF (30/46 Pages) Texas Instruments – 8/16-Channel, Constant Current LED Driver

TLC59291
SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
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Device Functional Modes (continued)
After being copied into the common shift register, new SID data are not available until new data are written into
the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID without
changing the on-off control data, reprogram the common shift register with the same data currently programmed
into the on-off data latch. When LAT goes high, the output on-off data is not changed, but new SID data are
loaded into the common shift register. LOD, LSD, OLD, PTW, TEF, ISF are shifted out of SOUT with each rising
edge of SCLK. The SID need to be read out after t_d4 or more from the device operation resumed from the power
save mode.
The SID reading must be delayed for a duration of t_D4 or more after the device resumes operation from the
power-save mode because SID does not indicate correct data during the power-save mode. The SID load
configuration and SID read timing are shown in Figure 10 and Figure 30, respectively.
Selected SID (16 bits) by SIDLD Data in the Control Data Latch
MSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT15 OUT14 OUT13 OUT12 OUT11
15
14
13
12
11
No data are loaded
into the MSB of the
common shift register
LSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT4 OUT3 OUT2 OUT1 OUT0
4
3
2
1
0
SID are loaded to the
common shift register
at the rising edge of
LAT when the common
shift register MSB is 0.
SOUT
MSB = ‘0’
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Bit
15
14
13
12
11
16
15
14
13
12
11
LSB
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
4
3
2
1
0
4
3
2
1
0
Common Shift Register (17 Bits)
Figure 30. SID Load Configuration
SIN
SLCK
SIDLD
1/0 BIT
00b
01b
10b
11b
Table 4. SID Load Assignment
SELECTED
DETECTOR
CHECKED OUTn
No detector selected
LED open detection
(LOD)
LED short detection
(LSD)
Output leakage
detection (OLD)
—
OUT0
OUT1
∙∙∙
OUT14
OUT15
OUT0
OUT1
∙∙∙
OUT14
OUT15
OUT0
OUT1
∙∙∙
OUT14
OUT15
BIT NUMBER
LOADED INTO
COMMON SHIFT
REGISTER
No data loaded
0
1
∙∙∙
14
15
0
1
∙∙∙
14
15
0
1
∙∙∙
14
15
DESCRIPTION
The data in the common shift register are not changed.
The data in the common shift register are updated with LOD or TEF data.
All bits '1' = device junction temperature (T_J) is high (T_J > T_TEF) and all
outputs are forced off by the thermal shutdown function.'1 = OUTn shows
lower voltage than the LED open detection threshold (V_LOD).
0 = normal operation.
The data in the common shift register are updated with LSD or PTW data.
All bits '1' = device junction temperature (T_J) is high (T_J > T_PTW).
1 = OUTn shows higher voltage than the LED short detection threshold
(V_LSD) selected by LSDVLT.
0 = normal operation.
The data in the common shift register are updated with OLD or ISF data.
All bits '1' = IREF pin is shorted to GND with low impedance.
1 = OUTn is leaking to GND with greater than 3µA.
0 = normal operation.
30
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