DRV3202-Q1 Datasheet, PDF (31/41 Pages) Texas Instruments – DRV3202-Q1 3-Phase Brushless Motor Driver

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ITEMS
V_CC – Overcurrent
Motor – Overcurrent
V_DD – Overvoltage
V_DD – Undervoltage
Thermal Shut Down
Watchdog
EEPROM Data Check
Clock Monitor
CAN Overcurrent
SPI
DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
Table 1. Error Detection (continued)
SPI
Error Bit (V_CC)
Error Bit (OVAD)
Error Bit (VDO)
–
Error Bit (TD)
–
Error Bit (EEP)
–
Error Bit (CCD)
Error Bit (SPI)
PRE-DRIVER
–
STOP
–
STOP
STOP
–
–
–
–
–
FAULT SIGNAL
H
H
L
L
H
L
L
L
L
L
RES
H
H
H
L
H
L
H
L
H
H
7.3 Device Functional Modes
Table 2. Motor Overcurrent Truth Table
RES
0
1
OVCR
–
0
1
MOTOR OVERCURRENT
–
–
0
1
OVAD
0 (Clear)
0 (Clear)⁽²⁾⁽³⁾
Keep
1 (Set)
PRE-DRIVER ENABLE OR DISABLE
Disable ⁽¹⁾
Enable
Enable
Disable
(1) The CTLEN goes to Hi-Z because the external CPU will not drive it when RES = 0, then all the pre-drivers are turned off because
CTLEN is internally pulled down.
(2) The OVAD is not set, even if a motor overcurrent error is generated during OVCR = 0.
(3) The OVAD is cleared if OVCR = 0 even when the motor overcurrent error is generated.
7.4 Register Maps
Waiting Time From b9 Through b8
CS
DIN
b15~b10 b9~b8
b7~b0
Select Diagnosis or Command Register
From b15 Through b10
Command Input or Diagnosis Result Output From b7 Through b0
DOUT
b7~b0
Echo Back of b14~b9
Figure 33. SPI Bit Sequence
Table 3. SPI Bit Map (DIN)
ITEM
B15
B14
B13
B12
B11
B10
B9
COMMAND1
0
0
0
0
0
1
–
COMMAND2
0
0
0
0
1
0
–
COMMAND3
0
0
0
0
1
1
–
B8
B7
B6
–
SHM
SRT
–
AG1
AG0
–
–
–
Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: DRV3202-Q1
B5
B4
B3
B2
B1
B0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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