DRV3202-Q1 Datasheet, PDF (20/41 Pages) Texas Instruments – DRV3202-Q1 3-Phase Brushless Motor Driver

Not Recommended for New Designs
DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
Feature Description (continued)
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Vbgr = 2.325 V
(+0.75 V / ± 0.25 V)
VDD Undervoltage
Detection
VCC
R1
R2
Band Gap _{VHS = 0.1 V}
Regulator _{(+0.75 V / ± 0.05 V)}
VLVD
Clock
Monitor
VCC Low
Voltage Detection
(NMI)
WDEN
Watch Dog Timer
WDEN
Open: Enable
High: Disable
Disable During
Power On Reset
Power On Reset
Reset Logic
VCC
R_RES
3k
RES
100 pF
Option
PRN
From CPU
VNMI: Lower Threshold Voltage
VHS: Hysteresis Voltage
Figure 14. Watchdog Block Diagram
7.2.2 Serial Port I/F
The SPI is used to receive an input byte from CPU and to transmit an output byte to CPU. Four signals are
utilized according to the timing chart of Figure 15.
LSB
MSB
CS
CK
Register
Parallel Output
Parallel Input
DIN
MSB First
SCK
/16
Serial input
CK
Parallel Output
Shift Register
(16 bits)
Parallel Input
Serial Output
/16
Parallel Output
Output Latch
Parallel Input
EN
(Transparent if EN = High)
LSB
MSB
Figure 15. Block Diagram of SPI
DOUT
MSB First
Internal
Diagnosis Register
20
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