DRV3202-Q1 Datasheet, PDF (21/41 Pages) Texas Instruments – DRV3202-Q1 3-Phase Brushless Motor Driver

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DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
Feature Description (continued)
• CS – Chip Select
– This input signal is utilized to select this IC by CPU.
– This input signal is normally high and the communication is possible only when it is forced low.
– When this input signal falls, the communication between this IC and the CPU starts.
– Transmitted data is latched and the DOUT pin comes out of high impedance.
– When this input signal rises, the communication stops.
– The DOUT pin goes into high impedance. Then, the internal input register updates with the received bits
(only if the clock pulse numbers are right and the key bit of the DIN signals is correct).
– The next falling edge starts another communication.
– There is a minimum waiting time between two communications (T_wait).
– The pin has an internal pullup.
• SCK – Synchronization Serial Clock
– This input signal is utilized to synchronize the communication by CPU.
– It is normally high and the correct clock pulse number is 16.
– At each falling edge, the CPU writes a new bit on the DIN input and this IC writes a new bit on the DOUT
pin. At each rising edge, this IC reads the new bit on the DIN pin and the CPU reads the new bit on the
DOUT pin.
– The maximum clock frequency is 4 MHz.
– The pin has an internal pullup.
• DIN – Serial Input Data
– This input signal is used to receive 16-bit data.
– The bits are received in order from the MSB (first) to the LSB (last).
– The pin has an internal pullup.
• DOUT – Serial Output Data
– This output signal is used to transmit 16-bit data.
– It is a 3-state output and it is in high impedance mode when CS is high.
– The serial data bits are transmitted in order from the MSB (first) to the LSB (last).
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