DRV3202-Q1 Datasheet, PDF (13/41 Pages) Texas Instruments – DRV3202-Q1 3-Phase Brushless Motor Driver

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VB
Not Recommended for New Designs
DRV3202-Q1
SLVSBJ4B – OCTOBER 2012 – REVISED JULY 2016
Do not switch to RES LOW
when the VCC LOW time
is less than tRES.
VNMI+VHS
VCC
VSTN
tRES
Ignore transient voltage falling
NMI
(Internal signal)
RES is HIGH after tON from NMI-HIGH
if internal clock is not generated
(In case of malfunction).
Switch to NMI-LOW after tRES delay
when VCC is lower than VNMIL
RES signal should remain in low voltage
(< -0.4 V) and in this case, controlled CPU
should be in
tRH
tRES
RES is HIGH after tON from of NMI-HIGH.
RES
PRN
tON
tRL
RES is LOW at NMI-LOW. tON
Pwth
tOFF
Detecting only rising edge of PRN signal Switch to RES LOW if PRN stays at a High or LOW
level.
VNMI
tRES
RES is LOW at NMI-LOW.
If WDEN is LOW (or OPEN),
and there is abnormal PRN:
RES is active.
If WDEN is HIGH,
and there is abnormal PRN:
no operation.
WDEN
NOTE: WDEN = High, V_CC undervoltage condition sets RES = Low
Figure 1. Watchdog Timing Chart
T_lead T_pw
T_pw
T_lag
T_wait
CS
SCK
DIN
DOUT Hi-Z
MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
T_h
T_su
MSB D14 D13 D12 D11 D10 D9 D8 ^{D7 D6} D5 D4 D3 D2 D1 LSB
T_en
T_del
T_dis
Figure 2. SPI AC Timing Definition
Hi-Z
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