TDA2HA-17 Datasheet, PDF (308/380 Pages) Texas Instruments – TDA2x ADAS Applications Processor 17mm Package (AAS Package) Silicon Revision 2.0

TDA2HA-17, TDA2HG-17
SPRS952A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
(7) Maximum R_eff from SMPS to Processor.
(8) Maximum Loop Inductance for decoupling capacitor.
NOTE
For power IC which can support more than 10uF close to processor, a bulk capacitor of at
least 22uF is strongly recommended for VDD_MPU power domains.
8.3.5 Power Supply Mapping
TPS65917 or TPS659039 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
• TI has validated their use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
• Support for power sequencing requirements (refer to Section 5.9 Power Supply Sequences)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
• The AVS voltage of active rail in the combined rail needs to be used to set the power supply
• The decoupling capacitance should be set according to the active rail in the combined rail
Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS659039 PMIC.
Table 8-4. TPS659039 Power Supply Connections
SMPS
SMPS1/2/3⁽²⁾
SMPS3⁽²⁾
Valid Combination
1:
Reference Platform
vdd_mpu
Free (DDR Memory)
Valid Combination
2:
MPU Centric
vdd_mpu
Free (DDR Memory)
Valid Combination
3:
DSPEVE Centric⁽³⁾
vdd_mpu, vdd_gpu,
vdd_iva
Free (DDR Memory)
Valid Combination
4: IVA Centric
vdd_mpu
Free (DDR Memory)
TPS659039 Current
Rating Limitation ⁽⁴⁾
(5)
SMPS1/2: 6A
SMPS1/2/3: 9A
SMPS3: 3A
SMPS4/5
vdd_dspeve
vdd_dspeve,
vdd_gpu, vdd_iva
vdd_dspeve
vdd_dspeve,
vdd_gpu
SMPS4/5: 4A
SMPS6
vdd_gpu
vdd
vdd
vdd
SMPS6: 2-3A
(BOOST_CURRENT
=0/1)
SMPS7
vdd
Free
Free
Free
2A
SMPS8
vdd_iva
Free
Free
vdd_iva
1A
SMPS9
vdds18v
vdds18v
vdds18v
vdds18v
1A
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Dual phase (SMPS1/2) can be used as long as the peak power consumption is maintained below the SMPS1/2 capacity
(a) For the latest rated output current specifications for the TPS659039 device, please refer to the PMIC data manual.
(b) MPU power consumption is highly system dependent. A detailed power consumption estimate must be performed to confirm
compatibility. Example: Single vs Dual MPU, OPP_NOM vs OPP_OD vs OPP_HIGH, TPS659039 configured with V_I≥3V vs V_I<3V,
etc. Contact your TI representative for details.
308 Applications, Implementation, and Layout
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