TDA2HA-17 Datasheet, PDF (127/380 Pages) Texas Instruments – TDA2x ADAS Applications Processor 17mm Package (AAS Package) Silicon Revision 2.0

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TDA2HA-17, TDA2HG-17
SPRS952A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name
GPU
GPU_FCLK1
GPU_FCLK2
HDMI PHY
I2C1
I2C2
I2C3
I2C4
I2C5
IEEE1500_2_OCP
GPU_ICLK
DSS_HDMI_PHY_
CLK
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
I2C3_ICLK
I2C3_FCLK
I2C4_ICLK
I2C4_FCLK
I2C5_ICLK
I2C5_FCLK
PI_L3CLK
IPU1
IPU1_GFCLK
IPU2
IVA
L3_INSTR
L3_MAIN
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
IPU2_GFCLK
IVA_GCLK
L3_CLK
L3_CLK1
L3_CLK2
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
MAILBOX1
MAILBOX2
MAILBOX3
MAILBOX4
MAILBOX5
MAILBOX6
MAILBOX7
MAILBOX8
MAILBOX9
MAILBOX1_FLCK
MAILBOX2_FLCK
MAILBOX3_FLCK
MAILBOX4_FLCK
MAILBOX5_FLCK
MAILBOX6_FLCK
MAILBOX7_FLCK
MAILBOX8_FLCK
MAILBOX9_FLCK
Clock
Type
Func
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int &
Func
Int &
Func
Int &
Func
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Max. Clock
Allowed (MHz)
GPU_CLK
GPU_CLK
266
38.4
PRCM Clock Name
GPU_CORE_GCLK
GPU_HYD_GCLK
GPU_L3_GICLK
HDMI_PHY_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
CORE_X2_CLK
FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
IPU_L3_GICLK
CORE_X2_CLK
96
IPU_96M_GFCLK FUNC_192M_CLK
266
L3INIT_L3_GICLK
CORE_X2_CLK
425.6
425.6
IVA_GCLK
L3_CLK
L3_CLK
L3_CLK
133
133
133
133
38.4
266
266
266
266
266
266
266
266
266
IPU1_GFCLK
IPU2_GFCLK
IVA_GCLK
L3INSTR_L3_GICLK
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L4CFG_L3_GICLK
L4PER_L3_GICLK
L4PER2_L3_GICLK
L4PER3_L3_GICLK
WKUPAON_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
DPLL_ABE_X2_CL
K
CORE_IPU_ISS_B
OOST_CLK
CORE_IPU_ISS_B
OOST_CLK
IVA_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_IVA
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
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Specifications 127