TDA2HA-17 Datasheet, PDF (300/380 Pages) Texas Instruments – TDA2x ADAS Applications Processor 17mm Package (AAS Package) Silicon Revision 2.0

TDA2HA-17, TDA2HG-17
SPRS952A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
3. Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
5. Place all voltage and gnd plane vias “as close as possible” to point of use (i.e. Dcap pads, component
power pins, etc.).
6. Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the MPU power domain has yielded the vdd_mpu Impedance vs Frequency
response shown in Section 8.3.7.2, vdd_mpu Example Analysis. As the example shows the overall MPU
PDN R_eff meets the maximum recommended PDN resistance of 10mΩ.
8.2.5 System ESD Generic Guidelines
8.2.5.1 System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-
resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in Figure 8-16) from connector to external protection because the interconnect may see between 15-
A to 30-A current in a short period of time during the ESD event.
300 Applications, Implementation, and Layout
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