TDA2HA-17 Datasheet, PDF (1/380 Pages) Texas Instruments – TDA2x ADAS Applications Processor 17mm Package (AAS Package) Silicon Revision 2.0

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TDA2HA-17, TDA2HG-17
SPRS952A – DECEMBER 2015 – REVISED APRIL 2016
TDA2x ADAS Applications Processor
17mm Package (AAS Package)
Silicon Revision 2.0
1 Device Overview
1.1 Features
1
• Architecture Designed for ADAS Applications
• Video, Image, and Graphics Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Multiple Video Input and Video Output
• ARM® Cortex®-A15 Microprocessor Subsystem
• Up to 2 C66x™ Floating-Point VLIW DSP
– Fully Object-Code Compatible With C67x™ and
C64x+™
– Up to Thirty-two 16 × 16-Bit Fixed-Point
Multiplies per Cycle
• Up to 2.5MB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• DDR2/DDR3/DDR3L Memory Interface (EMIF)
Module
– Supports up to DDR2-800 and DDR3-1066
– Up to 2GB Supported
• Two ARM® Dual Cortex®-M4 Image Processing
Units (IPUs)
• Vision AccelerationPac
– Up to Two Embedded Vision Engines (EVEs)
• IVA-HD Subsystem
• Display Subsystem
– Display Controller With DMA Engine and Three
Pipelines
– HDMI™ Encoder: HDMI 1.4a and DVI 1.0
Compliant
• 2D-Graphics Accelerator (BB2D) Subsystem
– Vivante™ GC320 Core
• Video Processing Engine (VPE)
• Dual-Core PowerVR® SGX544™ 3D GPU
• Two Video Input Port (VIP) Modules
– Support for up to 7 Multiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
Controller
• 2-Port Gigabit Ethernet (GMAC)
• Dual Controller Area Network (DCAN) Modules
– CAN 2.0B Protocol
• PCI-Express® 2.0 Port With Integrated PHY
– Single Port With 1 Lane at 5.0 Gbps
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces
(MCSPIs)
• Quad SPI Interface (QSPI)
• Five Inter-Integrated Circuit (I²C) Ports
• Multichannel Audio Serial Port (MCASP)
• Up to 247 General-Purpose I/O (GPIO) Pins
• Real-Time Clock Subsystem (RTCSS)
• Devise security features
– Hardware Crypto accelerators and DMA
– Firewalls
– JTAG lock
– Secure keys
– Secure ROM and boot
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• Automotive AEC-Q100 Qualified
• 28-nm CMOS Technology
• 17 mm × 17 mm, 0.65-mm Pitch, 625-Pin BGA
(AAS)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.