THS4271-EP Datasheet, PDF (28/44 Pages) Texas Instruments – LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE VOLTAGE FEEDBACK AMPLIFIER

THS4271-EP
SGLS270C – DECEMBER 2004 – REVISED APRIL 2010
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a
high-frequency amplifier like the THS4271 requires
careful attention to board layout parasitics and
external component types.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-mF
de-coupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (2.2-mF to 6.8-mF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PCB.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4271. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep their
leads and PC board trace length as short as
possible. Never use wire-wound type resistors in
a high frequency application. Since the output pin
and inverting input pin are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components,
such
as
noninverting
input-termination resistors, should also be placed
close to the package. Where double-side
component mounting is allowed, place the
feedback resistor directly under the package on
the other side of the board between the output
and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create
significant time constants that can degrade
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performance. Good axial metal-film or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2 kΩ, this parasitic capacitance can add a pole
and/or a zero below 400-MHz that can effect
circuit operation. Keep resistor values as low as
possible, consistent with load driving
considerations. A good starting point for design is
to set the R_f to 249-Ω for low-gain, noninverting
applications. Doing this automatically keeps the
resistor noise terms low, and minimizes the effect
of their parasitic capacitance.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set R_ISO from the
plot of recommended R_ISO vs capacitive load.
Low parasitic capacitive loads (<4 pF) may not
need an R_(ISO), since the THS4271 is nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
R_(ISO) are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss
intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance
environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined based on board
material and trace dimensions, a matching series
resistor into the trace from the output of the
THS4271 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB
attenuation of a doubly terminated transmission
line is unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of
R_(ISO) vs capacitive load. This does not preserve
signal integrity or a doubly-terminated line. If the
input impedance of the destination device is low,
there is some signal attenuation due to the
voltage divider formed by the series output into
the terminating impedance.
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