THS4271-EP Datasheet, PDF (27/44 Pages) Texas Instruments – LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE VOLTAGE FEEDBACK AMPLIFIER

THS4271-EP
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R_S
E_RS
4kTR_S
4kT
R_g
E_NI
I_BN
THS4271/THS4275
+
E_O
_
R_f
E_RF
R_g
I_BI
4kTR_f
4kT = 1.6E-20J
at 290K
Figure 88. Noise Analysis Model
The total output spot noise voltage can be computed
as the square of all square output noise voltage
contributors. Equation 4 shows the general form for
the output noise voltage using the terms shown in
Figure 88:
Ǹǒ Ǔ E_O +
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S NG² ) ^ǒI_BIR_f^Ǔ2 ) 4kTR_fNG
(4)
Dividing this expression by the noise gain
[NG=(1+ R_f/R_g)] gives the equivalent input-referred
spot noise voltage at the noninverting input, as shown
in Equation 5:
Ǹ ǒ Ǔ _{EO +}
2
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S )
I_BIR_f
NG
)
4kTR
NG
f
(5)
Evaluation of these two equations for the circuit and
component values shown in Figure 76 will give a total
output spot noise voltage of 12.2 nV/√Hz and a total
equivalent input spot noise voltage of 6.2 nV/√Hz.
This includes the noise added by the resistors. This
total input-referred spot noise voltage is not much
higher than the 3-nV/√Hz specification for the
amplifier voltage noise alone.
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4271 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier open-loop output resistance is
considered, this capacitive load introduces an
SGLS270C – DECEMBER 2004 – REVISED APRIL 2010
additional pole in the signal path that can decrease
the phase margin. When the primary considerations
are frequency response flatness, pulse response
fidelity, or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4271. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4271 output pin (see the Board Layout
Guidelines section).
The criterion for setting this R_(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load. For a gain of +2, the frequency response at the
output pin is already slightly peaked without the
capacitive load, requiring relatively high values of
R_(ISO) to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
0.5
0
-0.5
R_(ISO) = 25 Ω C_L = 10 pF
-1
R_(ISO) = 15 Ω C_L = 100 pF
-1.5
R_(ISO) = 10 Ω C_L = 50 pF
-2
-2.5
R_L = 499 Ω
V_S =±5 V
-3
1M
10 M
f - Frequency - Hz
100 M
Figure 89. Isolation Resistor Diagram
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