CC2560A_16 Datasheet, PDF (28/51 Pages) Texas Instruments – Dual-Mode Bluetooth Controller

CC2560A NRND; CC2564 NRND
CC2560A, CC2560B, CC2564, CC2564B
SWRS121E – JULY 2012 – REVISED JANUARY 2016
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• The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start
with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each
channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for
sample sizes up to 24 bits.
• Data_In and Data_Out are not required to be the same length.
• The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for
permanent Hi-Z, regardless of the data output. This configuration allows the device to be a bus slave in
a multislave PCM environment. At power up, Data_Out is configured as Hi-Z.
6.4.3.4 Frame Idle Period
The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of
the frame, after all data are transferred.
The device supports frame idle periods both as master and slave of the codec bus.
When the device is the master of the interface, the frame idle period is configurable. There are two
configurable parameters:
• Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of
the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.
• Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time
is given in multiples of clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.
Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts
60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period
ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the
beginning of the idle period.
Figure 6-12 shows the frame idle timing.
Frame_Sync
Frame period
Data_In
Data_Out
Clock
Frame idle
Clk_Idle_Start
Clk_Idle_End
Figure 6-12. Frame Idle Period
frmidle_swrs064
6.4.3.5 Clock-Edge Operation
The codec interface of the device can work on the rising or the falling edge of the clock and can sample
the Frame_Sync signal and the data at inversed polarity.
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Detailed Description
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