CC2560A_16 Datasheet, PDF (21/51 Pages) Texas Instruments – Dual-Mode Bluetooth Controller

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CC2560A NRND; CC2564 NRND
CC2560A, CC2560B, CC2564, CC2564B
SWRS121E – JULY 2012 – REVISED JANUARY 2016
6 Detailed Description
6.1 Overview
The CC256x architecture comprises a DRP™ and a point-to-multipoint baseband core. The architecture is
based on a single-processor ARM7TDMIE^® core. The device includes several on-chip peripherals to
enable easy communication with a host system and the Bluetooth BR/EDR/LE core.
6.2 Functional Block Diagram
CC256x
PCM/I2S
I/O
interface
Coprocessor
(See Note)
BR/EDR
main processor
Modem
arbitrator
DRP
2.4-GHz
band pass filter
UART
HCI
Power
management
Clock
management
Power Shutdown Slow Fast
clock clock
SWRS121-001
Note: The following technologies and assisted modes cannot be used simultaneously with the coprocessor: Bluetooth
LE, ANT, assisted HFP 1.6 (WBS), and assisted A2DP. One and only one technology or assisted mode can be used
at a time.
Figure 6-1. CC256x Functional Block Diagram
6.3 Clock Inputs
This section describes the available clock inputs. For specifications, see Section 5.7.2, Clock
Specifications.
6.3.1 Slow Clock
An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the
host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The
accuracy of the slow clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the
Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms)
following the release of nSHUTD.
6.3.2 Fast Clock Using External Clock Source
An external clock source is fed to an internal pulse-shaping cell to provide the fast-clock signal for the
device. The device incorporates an internal, automatic clock-scheme detection mechanism that
automatically detects the fast-clock scheme used and configures the F_REF cell accordingly. This
mechanism ensures that the electrical characteristics (loading) of the fast-clock input remain static
regardless of the scheme used and eliminates any power-consumption penalty-versus-scheme used.
The frequency variation of the fast-clock source must not exceed ±20 ppm (as defined by the Bluetooth
specification).
The external clock can be AC- or DC-coupled, sine or square wave.
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Detailed Description
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