LMH0394_15 Datasheet, PDF (26/35 Pages) Texas Instruments – 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer

LMH0394
SNLS312M – AUGUST 2010 – REVISED JULY 2015
10 Layout
www.ti.com
10.1 Layout Guidelines
For information on layout and soldering of the WQFN package, please refer to the following application note: AN-
1187 Leadless Leadframe Package (LLP) (SNOA401).
The ST 424, 292, and 259 standards have stringent requirements for the input return loss of receivers, which
essentially specify how closely the input must resemble a 75-Ω network. Any non-idealities in the network
between the BNC and the equalizer will degrade the input return loss. Care must be taken to minimize
impedance discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this
trace is 75 Ω. Please consider the following PCB recommendations:
• Use surface mount components, and use the smallest components available. In addition, use the smallest
size component pads.
• Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.
• Select a board stack-up that supports both 75-Ω single-ended traces and 100-Ω loosely-coupled differential
traces.
• Place return loss components closest to the equalizer input pins.
• Maintain symmetry on the complementary signals.
• Route 100-Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
• Avoid sharp bends in the signal path; use 45° or radial bends.
• Place bypass capacitors close to each power pin, and use the shortest path to connect equalizer power and
ground pins to the respective power or ground planes.
10.2 Layout Example
Figure 22 and Figure 21 demonstrate the LMH0394EVM PCB layout. Ground and supply relief under the return
loss passive components and pads reduces parasitic - improving return loss performance. The solder mask for
the DAP is divided into four quadrants. Five via are placed such that they are in the boundary of the 4 quadrants.
This is done to ensure that the via are not covered by solder mask for improving solder quality. This practice
improves both thermal performance and soldering during board assembly.
Ground and V_CC relief under BNC landing pad
and return loss passive components
to achieve good return loss
Figure 21. LMH0394EVM Top Etch Layout
26
Submit Documentation Feedback
Product Folder Links: LMH0394
Copyright © 2010–2015, Texas Instruments Incorporated