LMH0394_15 Datasheet, PDF (14/35 Pages) Texas Instruments – 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer

LMH0394
SNLS312M – AUGUST 2010 – REVISED JULY 2015
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7.5 Programming
7.5.1 SPI Register Access
Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0394 provides
register access to all of its features along with a cable length indicator, programmable output de-emphasis,
programmable output common-mode voltage and swing, digital MUTE_REF, and launch amplitude optimization.
There are eight supported 8-bit registers in the device (see Table 1). The LMH0394 supports SPI daisy-chaining
among an unlimited number of LMH0394 devices. With SPI_EN set low, the device operates in pin mode and is
footprint compatible with the LMH0384, LMH0344, LMH0044, and LMH0074.
7.5.1.1 SPI Transaction Overview
Each SPI transaction to a single device is 16-bits long. The transaction is initiated by driving SS low, and
completed by returning SS high. The 16-bit MOSI payload consists of the read/write command (“1” for reads and
“0” for writes), the seven address bits of the device register (MSB first), and the eight data bits (MSB first). The
LMH0394 MOSI input data is latched on the rising edge of SCK, and the MISO output data is sourced on the
falling edge of SCK.
In order to facilitate daisy-chaining, the prior SPI command, address, and data are shifted out on the MISO
output as the current command, address, and data are shifted in on the MOSI input. For SPI writes, the MISO
output is typically ignored as “Don't Care” data. For SPI reads, the MISO output provides the requested read data
(after 16 periods of SCK). The MISO output is active when SS low, and tri-stated when SS is high.
7.5.1.2 SPI Write
The SPI write is shown in Figure 2. The SPI write is 16 bits long. The 16-bit MOSI payload consists of a “0” (write
command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the
LMH0394's MOSI input. After the SPI write, SS must return high. The prior SPI command, address, and data
shifted out on the MISO output during the SPI write is shown as “Don't Care” on the MISO output in Figure 2.
7.5.1.3 SPI Read
The SPI read is shown in Figure 3. The SPI read is 32 bits long, consisting of a 16-bit read transaction followed
by a 16-bit dummy read transaction to shift out the read data on the MISO output. The first 16-bit MOSI payload
consists of a “1” (read command), seven address bits, and eight “1”s which are ignored. The second 16-bit MOSI
payload consists of 16 “1”s which are ignored but necessary in order to shift out the requested read data on the
MISO output. The SS signal is driven low, and the first 16 bits are sent to the LMH0394's MOSI input. The prior
SPI command, address, and data are shifted out on the MISO output during the first 16-bit transaction, and are
typically ignored (this is shown as “Don't Care” on the MISO output in Figure 3. SS must return high and then is
driven low again before the second 16 bits (all “1”s) are sent to the LMH0394's MOSI input. Once again, the prior
SPI command, address, and data are shifted out on the MISO output, but this data now includes the requested
read data. The read data is available on the MISO output during the second 8 bits of the 16-bit dummy read
transaction, as shown by D7-D0 in Figure 3.
7.5.1.4 SPI Daisy-Chain Operation
The LMH0394 SPI controller supports daisy-chaining the serial data between an unlimited number of LMH0394
devices. Each LMH0394 device is directly connected to the SCK and SS pins on the host. However, only the first
LMH0394 device in the chain is connected to the host’s MOSI pin, and only the last device in the chain is
connected to the host’s MISO pin. The MISO pin of each intermediate LMH0394 device in the chain is connected
to the MOSI pin of the next LMH0394 device, creating a serial shift register.
This daisy-chain architecture is shown in Figure 10.
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