LMH0394_15 Datasheet, PDF (17/35 Pages) Texas Instruments – 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer

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Programming (continued)
LMH0394
SNLS312M – AUGUST 2010 – REVISED JULY 2015
48-bit SPI Transaction #1
48-bit SPI Transaction #2
(Device 3)
(Device 2)
(Device 1)
R/W Addr Data R/W Addr Data R/W Addr Data
MOSI
(host)
0
0x01
0x22
1
0x00
0xFF
0
0x00
0x10
MISO
(host)
X
XX
XX X XX
XX X XX
XX
(Device 3)
(Device 2)
(Device 1)
R/W Addr Data R/W Addr Data R/W Addr Data
1 0x7F 0xFF 1 0x7F 0xFF 1 0x7F 0xFF
0 0x01 0x22 1 0x00 0x88 0 0x00 0x10
Figure 13. SPI Daisy-Chain Read and Write Example
The following occurs at the end of the first transaction:
1. Write 0x22 to register 0x01 of Device 3.
2. Latch the data from register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 1.
In the second transaction, three dummy reads (each consisting of 16 “1”s) are shifted in, and the read data from
Device 2 (with value 0x88) appears on MISO in the 25th through 32nd clock cycles.
7.5.1.8 SPI Daisy-Chain Length Detection
A useful operation for the host may be to detect the length of the daisy-chain. This is a simple matter of shifting
in a series of dummy reads with a known data value (such as 0x5A). For an SPI daisy-chain of N LMH0394
devices, the known data value will appear on the host's MISO pin after N+1 writes. Assuming a daisy-chain of
three LMH0394 devices, the result of this operation is shown in Figure 14.
R/W Addr
MOSI
(host)
1
0x7F
MISO
(host)
X
XX
Data R/W Addr
0x5A 1 0x7F
XX X XX
Data R/W Addr
0x5A 1 0x7F
XX X XX
Data R/W Addr
0x5A 1 0x7F
XX 1 0x7F
Data
0x5A
0x5A
Figure 14. SPI Daisy-Chain Length Detection
7.5.1.9 Output Driver Adjustments and De-emphasis Setting
The output driver swing (amplitude), offset voltage (common-mode voltage), and de-emphasis level are
adjustable through SPI register 01h.
The output swing is adjustable through bits [7:6] of SPI register 01h. The default value for these register bits is
10b for a peak to peak differential output voltage of 700 mV_P-P. The output swing can be set for 400 mV_P-P,
600 mV_P‑P, 700 mV_P-P, or 800 mV_P-P.
The offset voltage is adjustable through bits [5:4] of SPI register 01h. The default value for these register bits is
10b for an output offset of 1.2 V. The output common-mode voltage may be adjusted in 200 mV increments, from
0.8 V to 1.2 V. It can be set to “11b” for the maximum offset voltage. At this maximum offset voltage setting, the
outputs are referenced to the positive supply and the offset voltage is around 1.35 V.
The output de-emphasis is turned on or off by bit 3 of SPI register 01h, and the de-emphasis level is set by bits
[2:1] of SPI register 01h. The output de-emphasis level may be set for 0 dB (for driving up to 10” FR4), -3 dB (for
driving 10-20” FR4), -5 dB (for driving 20-30” FR4), or -7 dB (for driving 30-40” FR4).
7.5.1.10 Launch Amplitude Optimization
The LMH0394 can compensate for attenuation of the input signal prior to the equalizer. This compensation is
useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and
is controlled by SPI register 02h.
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