DRV2625 Datasheet, PDF (25/77 Pages) Texas Instruments – DRV2625 Ultra Low Power Closed-Loop LRA/ERM Haptic Driver with Built-In Library

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Programming (continued)
DRV2625
SLOS879A – DECEMBER 2015 – REVISED DECEMBER 2015
7-bit slave address
R/W A
8-bit register address (N)
A
8-bit register data for address
(N)
A
8-bit register data for address
(N)
A
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Start
Stop
Figure 23. Typical I²C Sequence
The DRV2625 device operates as an I²C-slave 1.8-V logic thresholds, but can operate up to the V_DD voltage.
The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5
(8-bit) for reading.
8.6.3.4 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte R/W operations for all registers.
During multiple-byte read operations, the DRV2625 device responds with data one byte at a time and beginning
at the signed register. The device responds as long as the master device continues to respond with
acknowledges.
The DRV2625 supports sequential I²C addressing. For write transactions, a sequential I²C write transaction has
taken place if a register is issued followed by data for that register as well as the remaining registers that follow.
For I²C sequential-write transactions, the register issued then serves as the starting point and the amount of data
transmitted subsequently before a stop or start is transmitted determines how many registers are written.
8.6.3.5 Single-Byte Write
As shown in Figure 24, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C device address and the read-write bit. The read-write bit determines the direction of
the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I²C
device address and the read-write bit, the DRV2625 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the DRV2625 internal-memory address that is accessed. After
receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
Acknowledge
Acknowledge
Acknowledge
A6 A5 A4 A3 A2 A1 A0 W ACK A7 A6 A5 A4 A3 A2 A0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
condition
I²C device address
and R/W bit
Subaddress
Figure 24. Single-Byte Write Transfer
Data byte
Stop
condition
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