DRV2625 Datasheet, PDF (24/77 Pages) Texas Instruments – DRV2625 Ultra Low Power Closed-Loop LRA/ERM Haptic Driver with Built-In Library

DRV2625
SLOS879A – DECEMBER 2015 – REVISED DECEMBER 2015
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Programming (continued)
8.6.2.2 Overdrive Voltage-Clamp Programming
During closed-loop operation, the actuator feedback allows the output voltage to go above the rated voltage
during the automatic overdrive and automatic braking periods. The OD_CLAMP[7:0] parameter sets a clamp so
that the automatic overdrive is bounded. The OD_CLAMP[7:0] parameter also serves as the full-scale reference
voltage for open-loop operation. The OD_CLAMP[7:0] parameter always represents the maximum peak voltage
that is allowed, regardless of the mode.
NOTE
If the supply voltage (V_DD) is less than the overdrive clamp voltage, the output driver is
unable to reach the clamp voltage value because the output voltage cannot exceed the
supply voltage. If the rated voltage exceeds the overdrive clamp voltage, the overdrive
clamp voltage has priority over the rated voltage.
V_{(ERM _ clamp)} =
î ^± î 2'B&/$03> @ î W_{(DRIVE_TIME)} ±
î^±
t_{(DRIVE_TIME)} t_{(IDISS_TIME)} t_{(BLANKING_TIME)}
(9)
V_{(LRA_clamp)}= 21.22 × 10^± × OD _ CLAMP[7:0]
(10)
8.6.3 I²C Interface
8.6.3.1 TI Haptic Broadcast Mode
The DRV2625 device has a TI haptic broadcast mode where, if enabled using the I²C_BCAST_EN bit, will make
the device respond to the slave address 0x58 (7-bit) or 1011000 in binary. This mode is useful in the event that
multiple haptic drivers implementing the TI haptic broadcast mode as installed in the system. In such a scenario,
writing the GO bit to the 0x58 slave address will cause all haptic drivers to trigger the process at the same time.
8.6.3.2 I²C Communication Availability
The I²C protocol is available for read/write operations during Standby, and Active states.
8.6.3.3 General I²C Operation
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with
the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving
device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition
on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the
data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the
SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur
within the low time of the clock period. Figure 23 shows a typical sequence. The master device generates the 7-
bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device
then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge
clock period to indicate acknowledgment. When the acknowledgment occurs, the master transmits the next byte
of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All
compatible devices share the same signals through a bidirectional bus using a wired-AND connection.
The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word
transfers, the master generates a stop condition to release the bus. Figure 23 shows a generic data-transfer
sequence.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull-up resistors
between 660 O and 4.7 kO are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2625
supply voltage, V_DD.
NOTE
The DRV2625 slave address is 0x5A (7-bit), or 1011010 in binary.
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