TLC8044 Datasheet, PDF (23/32 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS

TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
PRINCIPLES OF OPERATION
output word length select
This block is used to define the output word length, which can be programmed to 8, 10, 12, or 16 bits through
the serial interface. An internal clip function is provided that can be used in unipolar or bipolar fashion. For
example, if an 8-bit output word length is selected, the output data on OP0 – OP15 is limited to the range 0 to
255 for unipolar clipping or – 128 to 127 for bipolar clipping. If the signal to this block exceeds the positive clip
level, the ORNG signal is forced high. In 8-, 10-, and 12-bit output modes, the output data bit OP15 functions
as an under range flag; i.e., it is driven high if the input signal is less than the negative clip level. OP15 also
functions as an under range signal in 16-bit unipolar clipping mode.
serial interface
The serial interface data is used to configure the device operation and to program internal data registers. Figure
14 shows a timing diagram of a serial write operation. A serial data stream applied to the SDI terminal is clocked
into the device on the rising edge of SCK. The data stream comprises 6 address bits and two 8-bit data words.
When this data has is shifted into the device, a pulse applied to SEN transfers the data to the appropriate internal
register.
Tables 5 and 6 define the internal register map for the device and control bit functionality, respectively. The first
4 addresses in Table 5 (address bit a5 = 0) are used to program setup registers and to provide a software reset
feature. The remaining eight entries in Table 5 define the address locations of internal data registers, and three
additional subaddresses are defined for the red, green, or blue registers. Address bits a1 and a0 select between
the red, green, and blue registers, as defined in Table 5. When a1 and a0 are set to 1, all three registers are
updated to the same date value, as specified in data words 1 and 2. Blank entries in Table 5 are taken as don’t
care values.
SCK
ÏÏ ^SDI
a5
a4
a3
a2 a1
a0 b7
b6 b5
b4 b3 b2
b1
b0
b7 b6 b5
b4 b3 b2
b1
ÏÏ ^b0
SEN
Address
Data Word 1
Data Word 2
Figure 14. Serial Interface Timing
system timing
System timing diagrams that relate the timing between taking an input sample, applying the related pixel offset
and shading coefficients, and the output of the digital video data are shown in Figures 1 and 2. These diagrams
show the overall latency of the device in both color and monochrome operating modes. Detailed digital timing
diagrams are shown in Figure 15, 16, and 17.
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