TLC8044 Datasheet, PDF (15/32 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS

TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
PRINCIPLES OF OPERATION
RGB channel multiplexer and sampler (continued)
The input structure can be set up for use in single-ended or fully differential mode, under control of the serial
interface data. The configuration shown in the system diagram is single ended, with the negative inputs tied to
the DAC, which is the buffered midpoint of the ADC reference chain. Differential mode can be used when an
amplifier with differential outputs is placed between the CCD image sensor and the TLC8044.
In color operation, the three-channel sampling system multiplexes the three channels to the ADC input in a
sequence defined by the VSMP input synchronization pulse. In monochrome operation, channel
synchronization between R, G, and B inputs is achieved through the serial interface.
analog-to-digital converter
The ADC is implemented using a 12-bit pipelined architecture which performs conversions at one half the MCLK
clock rate. The ADC full-scale range is defined by the voltages applied to terminals RT and RB, which should
be set to 3.75 V and 1.25 V respectively to give a full-scale range of 3.75 V -1.25 V = 2.5 V.
The ADC internal input is differential with an input signal of 2.5 V corresponding to full scale (output code FFF
hex) and -2.5 V corresponding to zero scale (output code 000 hex).
The RU and RL terminals are connected to extensions of the internal reference chain, which allow the 3.75-V
and 1.25-V levels to be derived from a 5-V reference applied between RU and RL. All reference terminals should
be capacitively decoupled externally.
The combination of the input multiplexer structure with the internal offset correction DACs accomodates a wide
range of input voltages. The relationships between input voltage levels (at the positive and negative inputs INP
and INN) and ADC full-scale and zero-scale results are shown in Tables 1 and 2 for a range of input offset
voltages for both single-ended and differential input modes. The tables also show the DAC correction voltage
and code required in each case.
The basic difference between single-ended and differential input modes is that a gain of 2 is applied to the input
signal between INP and INN in the single-ended case. Thus an input differential of 1.25 V is converted to a
full-scale ADC differential input of 2.5 V. Any residual offset present on the input signal is also gained by 2 in
the single-ended mode, resulting in the required DAC values shown in Table 1.
Table 1. Single-Ended Mode Input Voltage Ranges
INPUT
OFFSET
VOLTAGE
0.625
0
-0.625
FULL-SCALE
INPUT
VOLTAGE
VI(INP) VI(INN)
4.375 2.5
3.75
2.5
3.125 2.5
ZERO-SCALE
INPUT
VOLTAGE
VI(INP) VI(INN)
1.875 2.5
1.25
2.5
0.625 2.5
DAC
VOLTAGE
-1.25
0
1.25
DAC
CODE
(HEX)
17F
000
07F
Table 2. Differential Mode Input Voltage Ranges
DIFFERENTIAL
INPUT OFFSET
VOLTAGE
1.25
0
-1.25
FULL-SCALE
INPUT
VOLTAGE
VI(INP) VI(INN)
4.375 0.625
3.75 1.25
3.125 1.875
ZERO-SCALE
INPUT
VOLTAGE
VI(INP) VI(INN)
1.875 3.125
1.25 3.75
0.625 4.375
DAC
VOLTAGE
-1.25
0
1.25
DAC
CODE
(HEX)
17F
000
07F
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