TLC8044 Datasheet, PDF (19/32 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS

TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
PRINCIPLES OF OPERATION
correlated double sampling
Correlated double sampling is a circuit technique for reducing any correlated noise between the reset (black)
level and the video level of the CCD array. Referring to the block diagram shown in Figure 13(a), a sample of
the CCD output is taken and held at the reset level and another sample is taken and held at the video level. These
two levels are subtracted essentially nulling any common signal, and thereby minimizing the correlated noise
that exists at both the reset level and the video level. Figure 13(b) shows relative timing.
S/H
AMP
Video Out
VIN
(CCD Output)
S/H
AMP
+
Subtractor
–
Reset Out
Vout = Video Out – Reset Out
VIN
(CCD Output)
Reset Video
S/H
S/H
(a)
Reset (Black) Level
Video
Reset S/H
Reset Out
Video S/H
Video Out
ADC Clock
(b)
Figure 13. Samplified Correlated Double Sampling
correlated double sampling mode
In CDS mode, two samples are taken per channel within each pixel period. Figure 12 shows the timing diagram
for this mode of operation. The video signal is sampled during the reset phase and during the video information
with timing defined relative to the VSMP input. The difference between these two samples forms the input to
the ADC. The relative timing of the reset and video samples shown in Figure 12 is the default (post-reset)
condition. The timing of the reset sample relative to the video sample can be advanced by one or retarded by
one or two MCLK periods under control of the serial interface. Figure 1 shows a detailed video input timing
diagram with all four CDS timing options.
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