CC2650_16 Datasheet, PDF (22/59 Pages) Texas Instruments – Multistandard Wireless MCU

CC2650
SWRS158A – FEBRUARY 2015 – REVISED OCTOBER 2015
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5.22 Timing Requirements
MIN NOM MAX UNIT
Rising supply-voltage slew rate
0
100 mV/µs
Falling supply-voltage slew rate
Falling supply-voltage slew rate, with low-power flash settings⁽¹⁾
0
20 mV/µs
3 mV/µs
Positive temperature gradient in standby⁽²⁾
CONTROL INPUT AC CHARACTERISTICS⁽³⁾
No limitation for negative
temperature gradient, or
outside standby mode
5 °C/s
RESET_N low duration
SYNCHRONOUS SERIAL INTERFACE (SSI) ⁽⁴⁾
1
µs
S1 (SLAVE) ⁽⁵⁾
S2 ⁽⁵⁾
S3 ⁽⁵⁾
t_{clk_per}
t_{clk_high}
t_{clk_low}
SSIClk period
SSIClk high time
SSIClk low time
12
65024
system
clocks
0.5
t_{clk_per}
0.5
t_{clk_per}
(1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see
Figure 7-1) must be used to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
Section 5.13).
(3) T_A = –40°C to 85°C, V_DDS = 1.7 V to 3.8 V, unless otherwise noted.
(4) T_c = 25°C, V_DDS = 3.0 V, unless otherwise noted. Device operating as SLAVE. For SSI MASTER operation, see Section 5.23.
(5) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
5.23 Switching Characteristics
Measured on the TI CC2650EM-5XD reference design with T_c = 25°C, V_DDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
WAKEUP AND TIMING
Idle → Active
14
Standby → Active
151
Shutdown → Active
SYNCHRONOUS SERIAL INTERFACE (SSI) ⁽¹⁾
1015
S1 (TX only)⁽²⁾ t_{clk_per} (SSIClk period)
One-way communication to SLAVE
4
65024
S1 (TX and RX)⁽²⁾ t_{clk_per} (SSIClk period)
Normal duplex operation
S2 ⁽²⁾ t_{clk_high} (SSIClk high time)
S3 ⁽²⁾ t_{clk_low}(SSIClk low time)
(1) Device operating as MASTER. For SSI SLAVE operation, see Section 5.22.
(2) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
8
65024
0.5
0.5
UNIT
µs
µs
µs
system
clocks
system
clocks
t_{clk_per}
t_{clk_per}
S1
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
4 to 16 bits
LSB
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
22
Specifications
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