AM1808_16 Datasheet, PDF (22/265 Pages) Texas Instruments – AM1808 ARM® Microprocessor

AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
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Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
EMA_A[22] / MMCSD0_CMD /
PRU1_R30[30] / GP4[6]
A10
O
EMA_A[21] / MMCSD0_DAT[0] /
PRU1_R30[29] / GP4[5]
B10
O
EMA_A[20] / MMCSD0_DAT[1] /
PRU1_R30[28] / GP4[4]
A11
O
EMA_A[19] / MMCSD0_DAT[2] /
PRU1_R30[27] / GP4[3]
C10
O
EMA_A[18] / MMCSD0_DAT[3] /
PRU1_R30[26] / GP4[2]
E11
O
EMA_A[17] / MMCSD0_DAT[4] /
PRU1_R30[25] / GP4[1]
B11
O
EMA_A[16] / MMCSD0_DAT[5] /
PRU1_R30[24] / GP4[0]
E12
O
EMA_A[15] / MMCSD0_DAT[6] /
PRU1_R30[23] / GP5[15] / PRU1_R31[23]
C11
O
EMA_A[14] / MMCSD0_DAT[7] /
PRU1_R30[22] / GP5[14] / PRU1_R31[22]
A12
O
EMA_A[13] /PRU0_R30[21] / PRU1_R30[21]
/ GP5[13] / PRU1_R31[21]
D11
O
EMA_A[12] / PRU1_R30[20] / GP5[12] /
PRU1_R31[20]
D13
O
EMA_A[11] / PRU1_R30[19] / GP5[11] /
PRU1_R31[19]
B12
O
EMA_A[10] / PRU1_R30[18] / GP5[10] /
PRU1_R31[18]
C12
O
EMA_A[9] / PRU1_R30[17] / GP5[9]
D12
O
EMA_A[8] / PRU1_R30[16] / GP5[8]
A13
O
EMA_A[7] / PRU1_R30[15] / GP5[7]
B13
O
EMA_A[6] / GP5[6]
E13
O
EMA_A[5] / GP5[5]
C13
O
EMA_A[4] / GP5[4]
A14
O
EMA_A[3] / GP5[3]
D14
O
EMA_A[2] / GP5[2]
B14
O
EMA_A[1] / GP5[1]
D15
O
EMA_A[0] / GP5[0]
C14
O
EMA_BA[0] / GP2[8]
C15
O
EMA_BA[1] / GP2[9]
A15
O
EMA_CLK / PRU0_R30[5] / GP2[7] /
PRU0_R31[5]
B7
O
EMA_SDCKE / PRU0_R30[4] / GP2[6] /
PRU0_R31[4]
D8
O
EMA_RAS / PRU0_R30[3] / GP2[5] /
PRU0_R31[3]
A16
O
EMA_CAS / PRU0_R30[2] / GP2[4] /
PRU0_R31[2]
A9
O
EMA_CS[0] / GP2[0]
A18
O
EMA_CS[2] / GP3[15]
B17
O
EMA_CS[3] / GP3[14]
A17
O
EMA_CS[4] / GP3[13]
F9
O
EMA_CS[5] / GP3[12]
B16
O
EMA_A_RW / GP3[9]
D10
O
PULL ⁽²⁾
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
POWER
GROUP ⁽³⁾
B
DESCRIPTION
B
B
B
B
B
EMIFA address bus
B
B
B
B
B
B
B
B
B
B
B
EMIFA address bus
B
B
B
B
B
B
B
EMIFA bank address
B
B
EMIFA clock
B
EMIFA SDRAM clock enable
B
EMIFA SDRAM row address strobe
B
EMIFA SDRAM column address strobe
B
EMIFA SDRAM Chip Select
B
B
EMIFA Async Chip Select
B
B
B
EMIFA Async Read/Write control
22
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