AM1808_16 Datasheet, PDF (113/265 Pages) Texas Instruments – AM1808 ARM® Microprocessor

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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.11.3.2 Compatible JEDEC DDR2/mDDR Devices
Table 6-25 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this
interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2-400/mDDR-200 speed
grade DDR2/mDDR devices.
The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one
chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control
signals are shared just like regular dual chip memory configurations.
Table 6-25. Compatible JEDEC DDR2/mDDR Devices
NO. PARAMETER
1 JEDEC DDR2/mDDR Device Speed Grade⁽¹⁾
MIN
DDR2-400/mDDR-
200
MAX
2 JEDEC DDR2/mDDR Device Bit Width
3 JEDEC DDR2/mDDR Device Count⁽²⁾
x8
x16
1
2
(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.
(2) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories
UNIT
Bits
Devices
6.11.3.3 PCB Stackup
The minimum stackup required for routing the device is a six layer stack as shown in Table 6-26.
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size
of the PCB footprint.Complete stack up specifications are provided in Table 6-27.
LAYER
1
2
3
4
5
6
Table 6-26. Device Minimum PCB Stack Up
TYPE
Signal
Plane
Plane
Signal
Plane
Signal
DESCRIPTION
Top Routing Mostly Horizontal
Ground
Power
Internal Routing
Ground
Bottom Routing Mostly Vertical
Table 6-27. PCB Stack Up Specifications
NO. PARAMETER
MIN
TYP
1 PCB Routing/Plane Layers
6
2 Signal Routing Layers
3
3 Full ground layers under DDR2/mDDR routing region
2
4 Number of ground plane cuts allowed within DDR routing region
5 Number of ground reference planes required for each DDR2/mDDR routing layer
1
6 Number of layers between DDR2/mDDR routing layer and reference ground plane
7 PCB Routing Feature Size
4
8 PCB Trace Width w
4
8 PCB BGA escape via pad size
18
9 PCB BGA escape via hole size
8
10 Device BGA pad size⁽¹⁾
11 DDR2/mDDR Device BGA pad size⁽²⁾
12 Single Ended Impedance, Zo
13 Impedance Control⁽³⁾
50
Z-5
Z
(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.
(2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
MAX
0
0
75
Z+5
UNIT
Mils
Mils
Mils
Mils
Ω
Ω
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Peripheral Information and Electrical Specifications 113
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