AM1808_16 Datasheet, PDF (132/265 Pages) Texas Instruments – AM1808 ARM® Microprocessor

AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
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6.14.2.6 SATA Interface Clock Source requirements
A high-quality, low-jitter differential clock source is required for the SATA PHY. The SATA interface
requires a LVDS differential clock source to be provided at signals SATA_REFCLKP and
SATA_REFCLKN. The clock source should be placed physically as close to the processor as possible.
Table 6-47 shows the requirements for the clock source.
Table 6-47. SATA Input Clock Source Requirements
PARAMETER
Clock Frequency ⁽¹⁾
MIN
TYP
75
Jitter
Duty Cycle
40
Rise/Fall Time
700
(1) Discrete clock frequency points are supported based on the PLL multiplier used in the SATA PHY.
MAX
375
50
60
UNIT
MHz
ps pk-pk
%
ps
6.14.3 SATA Unused Signal Configuration
If the SATA interface is not used, the SATA signals should be configured as shown below.
SATA Signal Name
SATA_RXP
SATA_RXN
SATA_TXP
SATA_TXN
SATA_REFCLKP
SATA_REFCLKN
SATA_MPSWITCH
SATA_CP_DET
SATA_CP_POD
SATA_LED
SATA_REG
SATA_VDDR
SATA_VDD
SATA_VSS
Table 6-48. Unused SATA Signal Configuration
Configuration if SATA peripheral is not used
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
May be used as GPIO or other peripheral function
May be used as GPIO or other peripheral function
May be used as GPIO or other peripheral function
May be used as GPIO or other peripheral function
No Connect
No Connect
Prior to silicon revision 2.0, this supply must be connected to a static 1.2V nominal supply. For silicon
revision 2.0 and later, this supply may be left unconnected for additional power conservation.
Vss
132 Peripheral Information and Electrical Specifications
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