AM3715_17 Datasheet, PDF (212/280 Pages) Texas Instruments – Sitara ARM Microprocessors

AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
6.6 Serial Communications Interfaces
6.6.1 Multichannel Buffered Serial Port (McBSP)
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NOTE
For more information, see Multi-Channel Buffered Serial Port chapter of the AM/DM37x
Multimedia Device Technical Reference Manual (literature number SPRUGN4).
The Multichannel Buffered Serial Port (McBSP) provides a full duplex direct serial interface between the
chip and other devices in a system such as other application chips, codecs. It can accommodate a wide
range of peripherals and clocked frame oriented protocols (I2S, PCM, T ) due to its high level of versatility.
McBSP may support two types of data transfer at the system level:
• The full cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time.
The interface clock (clkx/clkr) activation edge (data/frame sync capture and generation) has to be
configured accordingly with the external peripheral (activation edge capability) and the type of data
transfer required at the system level.
Depending on the number of pins, McBSP supports either:
• 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins
• 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are
internally looped back, via software configuration, respectively to the clkr and fsr internal signals for
data receive.
McBSP1 supports the 6-pin mode. McBSP2, 3, 4, and 5 support only the 4-pin mode.
The following sections describe the timing characteristics for applications in normal mode (that is, McBSPx
connected to one peripheral) and T applications in multipoint mode.
6.6.1.1 McBSP Timing Conditions—Normal Mode
Table 6-46 through Table 6-70 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-36 through Figure 6-43).
Table 6-45. McBSP Timing Conditions—Normal Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance⁽¹⁾
(1) Buffer strength configuration:
– McBSP4 - Set #1: LB0 = 1.
– Otherwise: LB0 = 0.
VALUE
2
2
10
UNIT
ns
ns
pF
212 Timing Requirements and Switching Characteristics
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