AM3715_17 Datasheet, PDF (202/280 Pages) Texas Instruments – Sitara ARM Microprocessors

AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
Table 6-34. CPI Timing Requirements—ITU Mode^{(4) (5)}
NO.
ISP17
ISP18
ISP18
1 / t_c(pclk)
t_w(pclkH)
t_w(pclkL)
t_dc(pclk)
t_J(pclk)
PARAMETER
Frequency⁽¹⁾, input pixel clock cam_pclk
Typical pulse duration, input pixel clock cam_pclk high
Typical pulse duration, input pixel clock cam_pclk low
Duty cycle error, input pixel clock cam_pclk
Cycle jitter⁽³⁾, input pixel clock cam_pclk
OPP100
MIN
MAX
75
0.5P⁽²⁾
0.5P⁽²⁾
0.5*P⁽²⁾ -
3.465
0.0649*P
(2)
ISP23 t_su(dV-pclkH)
Setup time, input data cam_d[9:0] valid before input
pixel clock cam_pclk rising edge
1.82
ISP24 t_h(pclkH-dV)
Hold time, input data cam_d[9:0] valid after input pixel 1.82
clock cam_pclk rising edge
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_pclk period in ns
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.
(5) See Section 4.3.4, Processor Clocks.
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OPP50
MIN
MAX
45
0.5P⁽²⁾
0.5P⁽²⁾
0.5*P⁽²⁾ -
6.93
0.0649*P
(2)
3.25
UNIT
MHz
ns
ns
ns
ns
ns
3.25
ns
cam_xclki
ISP16
ISP15
ISP16
cam_pclk
ISP17
ISP18
ISP18
ISP23
ISP24
cam_d[9:0]
SOF
D(0)
D(n-1)
EOF
SOF
D(0)
D(n-1)
EOF
SWPS038-054
(1) The unused lines are grounded and the data bus is connected to the lower data lines. However, it is possible to shift the data to 0, 2,
or 4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in
10-bit mode.
(2) The parallel camera in ITU mode supports progressive camera modules.
(3) In cam_xclki, i can be equal to a or b. See Table 6-22 for ISP15 and ISP16 parameters.
Figure 6-29. CPI—ITU Mode
202 Timing Requirements and Switching Characteristics
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