TCA9534_16 Datasheet, PDF (21/38 Pages) Texas Instruments – Low Voltage 8-Bit I2C and SMBUS Low-Power I/O Expander with Interrupt Output and Configuration Registers

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TCA9534
SCPS197B – SEPTEMBER 2014 – REVISED NOVEMBER 2016
SCL
12346 78 9
Slave Address
Command Byte
Data to Register
SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A
Data
AP
Start Condition
R/W ACK From Slave
ACK From Slave
ACK From Slave
Data to
Register
Figure 30. Write to Configuration or Polarity Inversion Registers
8.6.3.1.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this
register address, the master sends a START condition again, followed by the slave address with the R/W bit set
to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA
bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
See Table 3 for the list of the internal registers and a description of each one.
If a read is requested by the master after a POR without first setting the command byte via a write, the device will
NACK until a command byte-register address is set as described above.
Figure 31 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Device (Slave) Address (7 bits)
Register Address N (8 bits)
Device (Slave) Address (7 bits)
Data Byte from Register N (8 bits)
S 0 1 0 0 A2 A1 A0 0 A B7 B6 B5 B4 B3 B2 B1 B0 A Sr 0 1 0 0 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 NA P
START
R/W=0 ACK
ACK Repeated START
R/W=1 ACK
Figure 31. Read from Register
NACK STOP
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data. See Figure 32.
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