CC3120MOD Datasheet, PDF (21/52 Pages) Texas Instruments – SimpleLink Wi-Fi CERTIFIED Network Processor Internet-of-Things Module Solution for MCU Applications

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5.13.3.1 Host SPI Interface Timing
Figure 5-8 shows the host SPI timing diagram.
CC3120MOD
SWRS205 – MARCH 2017
I2
CLK
I6
I7
MISO
MOSI
I8
Figure 5-8. Host SPI Timing
I9
SWAS032-017
Table 5-4. Host SPI Interface Timing Parameters
PARAMETER
NUMBER
DESCRIPTION
MIN
MAX
UNIT
I1
F ⁽¹⁾
I2
t_clk ^{(1) (2)}
I3
t_LP ⁽¹⁾
I4
t_HT ⁽¹⁾
I5
D ⁽¹⁾
I6
t_IS ⁽¹⁾
I7
t_IH ⁽¹⁾
I8
t_OD ⁽¹⁾
I9
t_OH ⁽¹⁾
Clock frequency at V_BAT = 3.3 V
Clock frequency at V_BAT = 2.3 V
Clock period
Clock low period
Clock high period
Duty cycle
RX data setup time
RX data hold time
TX data output delay
TX data hold time
50
45%
4
4
20
12
25
25
55%
20
24
MHz
ns
ns
ns
ns
ns
ns
ns
(1) The timing parameter has a maximum load of 20 pf at 3.3 V.
(2) Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. The nCS signal can be deasserted 10 ns after the
clock edge.
5.13.3.2 Flash SPI Timing
The CC3120MOD provides an interface for direct programming of the flash. Note that the time diagram
and interface parameters are provided as a reference. During normal operation, the Flash SPI should
remain unconnected. Figure 5-9 shows the Flash SPI timing diagram.
CLK
MISO
MOSI
I2
I6
I7
I8
Figure 5-9. Flash SPI Timing
I9
SWAS032-017
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Specifications
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