BQ40Z50 Datasheet, PDF (21/30 Pages) Texas Instruments – 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

bq40z50
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• Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
• Number of Shutdown Events
• Cell Balancing Time for Each Cell
(This data is updated every 2 hours if a difference is detected.)
• Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
SLUSBS8 – DECEMBER 2013
Authentication
The bq40z50 supports authentication by the host using SHA-1.
LED Display
The bq40z50 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a permanent
fail (PF) error code indication.
Power Modes
The bq40z50 supports three power modes to reduce power consumption:
• In NORMAL mode, the bq40z50 performs measurements, calculations, protection decisions, and data
updates in 250-ms intervals. Between these intervals, the bq40z50 is in a reduced power stage.
• In SLEEP mode, the bq40z50 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq40z50 is in a reduced power stage. The bq40z50
has a wake function that enables exit from SLEEP mode when current flow or failure is detected.
• In SHUTDOWN mode, the bq40z50 is completely disabled.
Configuration
Oscillator Function
The bq40z50 fully integrates the system oscillators and does not require any external components to support this
feature.
System Present Operation
The bq40z50 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system,
the bq40z50 detects this as system present.
Emergency Shutdown
For battery maintenance, the emergency shutdown feature enables a push button action connecting the
SHUTDN pin to shutdown an embedded battery pack system before removing the battery. A high-to-low
transition of the SHUTDN pin signals the bq40z50 to turn off both CHG and DSG FETs, disconnecting the power
from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by another
high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.
1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
In a 1-series cell configuration, VC4 is shorted to VC, VC2 and VC1. In a 2-series cell configuration, VC4 is
shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.
Cell Balancing
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing
mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
Copyright © 2013, Texas Instruments Incorporated
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