BQ40Z50 Datasheet, PDF (2/30 Pages) Texas Instruments – 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

bq40z50
SLUSBS8 – DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
T_A
–40°C to
85°C
PART
NUMBER
bq40z50
ORDERING INFORMATION
PACKAGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
RSM-32
RSM
bq40z50
ORDERING INFORMATION⁽¹⁾
TUBE ⁽²⁾
TAPE AND
REEL ⁽³⁾
bq40z50RSMT
bq40z50RSMR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units.
THERMAL INFORMATION
θ_{JA, High K}
θ_JC(top)
θ_JB
ψ_JT
ψ_JB
θ_JC(bottom)
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case(bottom) thermal resistance⁽⁷⁾
bq40z50
RSM (QFN)
32 Pins
47.4
40.3
14.7
0.8
14.4
3.8
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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