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BQ40Z50 Datasheet, PDF (12/30 Pages) Texas Instruments – 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager
bq40z50
SLUSBS8 – DECEMBER 2013
www.ti.com
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Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Conversion time
Resolution
Effective resolution
TEST CONDITION
Single conversion
Single conversion
Single conversion
Single conversion
No missing codes
With sign, tCONV = 31.25 ms
With sign, tCONV = 15.63 ms
With sign, tCONV = 7.81 ms
With sign, tCONV = 1.95 ms
MIN
TYP
MAX
UNIT
31.25
15.63
ms
7.81
1.95
16
Bits
14
15
13
14
Bits
11
12
9
10
CHG, DSG FET DRIVE
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
Output voltage
ratio
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,
10 MΩ between PACK and DSG
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,
10 MΩ between BAT and CHG
V(FETON)
V(FETOFF)
tR
tF
Output voltage,
VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
PACK and DSG, VBAT = 18 V
CHG and DSG on VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
BAT and CHG, VBAT = 18 V
Output voltage,
VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and
DSG
CHG and DSG off
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG
Rise time
VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL =
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and CL, 10 MΩ between PACK and DSG
VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL =
4.7 nF between CHG and BAT, 5.1 kΩ between CHG
and CL, 10 MΩ between BAT and CHG
Fall time
VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between DSG and PACK, 5.1 kΩ between DSG and CL,
10 MΩ between PACK and DSG
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7
nF between CHG and BAT, 5.1 kΩ between CHG and
CL, 10 MΩ between BAT and CHG
MIN
2.133
2.133
10.5
10.5
–0.4
–0.4
TYP
2.333
2.333
11.5
11.5
200
200
40
40
MAX
2.433
2.433
12
12
0.4
0.4
500
500
300
200
UNIT
—
V
V
µs
µs
PCHG FET DRIVE
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
V(FETON)
Output voltage,
PCHG on
V(FETOFF)
Output voltage,
PCHG off
tR
Rise time
TEST CONDITION
VPCHG(ON) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
VPCHG(OFF) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥ 8 V, CL =
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
MIN
6
–0.4
TYP
MAX
UNIT
7
8
V
0.4
V
40
200
µs
12
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