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THS6032_14 Datasheet, PDF (20/35 Pages) Texas Instruments – LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER
THS6032
SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com
DGND OUTPUT AMPLITUDE
vs
FREQUENCY
3
2
VO(PP) = 0.2 V
1
0
−1
−2
VO(PP) = 2 V
−3
VCC(H) = ± 15 V
−4
VCC(L) = ± 5 V
RL = 25 Ω
−5 VSD = +10 V
VI = DGND Pin
−6
100 k
1M
10 M
f − Frequency − Hz
100 M
Figure 45.
The second design consideration is due to transistors Q5 and Q6. These transistors ensure that the +IN to –IN
voltage separation is less than a VBE drop (about 0.7 V). This protects the other transistors, Q1 to Q4, from
saturating during fast transients. Transistors Q5 and Q6 also enhance the slew rate capabilities of the THS6032.
When a fast transient is applied to the input, these transistors quickly apply the currents to the active load stages.
A design issue with this setup is that while in shutdown mode, a large enough signal being applied to the input
pins may turn on these transistors. Once the input voltage differential between the +IN and –IN pins reaches
±0.7-V, transistors Q5 and Q6 turn on, applying the difference signal to the rest of the amplifier circuitry. Because
these two transistors are designed for much higher performance levels than the shutdown circuitry transistors
(QS3 and QS4), they will become dominant and the difference input signal will be utilized instead of the DGND
signal. Because the external negative feedback resistor path is still connected around the amplifier, this
difference input signal will be amplified just like a normal amplifier is designed to do (see Figure 46). As long as
the +IN and –IN input signals are kept below ±0.7 V, the isolation from input-to-output is very high, as shown in
the Shutdown Isolation vs Frequency graphs (see Figure 30 and Figure 31).
To ensure proper shutdown functionality of the THS6032, it is important to keep the DGND voltage noise-free.
Additionally, the +IN and –IN signals should be limited to less than ±0.7 V during shutdown mode. This will
ensure proper line termination functionality while conserving power.
SHUTDOWN FEEDTHROUGH
7
6
G=5
5
G=2
G = +1;
G = −1
4
3
2
VCC(H)= ± 15 V
VCC(L)=± 5 V
1
RL = 25 Ω
VSD = 5 V
0
0
2
4
6
8
10
VIN − Input Voltage − V
Figure 46.
20
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