THS6032_14 Datasheet, PDF (16/35 Pages) Texas Instruments – LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

THS6032
SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
9
T_J = 125°C
8
DWP
7
θ_JA = 21.5°C/W
6
VFP
θ_JA = 30°C/W
5
GQE
θ_JA = 37.8°C/W
4
3
2
DWP
1
θ_JA = 43.9°C/W
No Solder Utilized
0
−40 −20 0
20 40 60 80 100
T_A − Free-Air Temperature − °C
Figure 40. Maximum Power Dissipation vs Free-Air Temperature
PCB DESIGN CONSIDERATIONS
Proper PCB design techniques in two areas are important to assure proper operation of the THS6032. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6032 is a
high-speed part, the following guidelines are recommended.
• Ground plane – It is essential that a ground plane be used on the board to provide all components with a
low-inductance ground connection. Although a ground connection directly to a terminal of the THS6032 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low-inductance ground to the device substrate to minimize internal crosstalk, and
it provides a path for heat removal.
• Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This is
especially true in the noninverting configuration. An example of this can be seen in Figure 41, which shows
what happens when a 2.2 pF capacitor is added to the inverting input terminal in the noninverting
configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of the
error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While the
device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is because
the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in the
noninverting configuration. This can be seen in Figure 42, where a 27-pF capacitor adds only 2.5 dB of
peaking. In general, as the gain of the system increases, the output peaking due to this capacitor decreases.
While this can initially appear to be a faster and better system, overshoot and ringing are more likely to occur
under fast transient conditions. Therefore, proper analysis of adding a capacitor to the inverting input node
should always be performed to ensure stable operation.
16
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