BQ4010_14 Datasheet, PDF (2/16 Pages) Texas Instruments – 8 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

bq4010/Y/LY
Not Recommended For New Designs
SLUS116A – MAY 1999 – REVISED JUNE 2007
NAME
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
A₁₁
A₁₂
CE
DQ₀
DQ₁
DQ₂
DQ₃
DQ₄
DQ₅
DQ₆
DQ₇
NC
OE
V_CC
V_SS
WE
TERMINAL
NUMBER
10
9
8
7
6
5
4
3
25
24
21
23
2
20
11
12
13
15
16
17
18
19
1
26
22
28
14
27
DEVICE INFORMATION
Table 1. TERMINAL FUNCTIONS
I/O
DESCRIPTION
I
I
I
I
I
I
I
Address inputs
I
I
I
I
I
I
I
Chip-enable input
I/O
I/O
I/O
I/O
Data input/output
I/O
I/O
I/O
I/O
-
No connect
I
Output enable input
I
Supply voltage input
-
Ground
I
Write enable input
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FUNCTIONAL DESCRIPTION
When power is valid, the bq4010/Y/LY operates as a standard CMOS SRAM. During power-down and power-up
cycles, the bq4010/Y/LY acts as a nonvolatile memory, automatically protecting and preserving the memory
contents.
Power-down/power-up control circuitry constantly monitors the V_CC supply for a power-fail-detect threshold V_PFD.
The bq4010 monitors for V_PFD = 4.62 V typical for use in 5-V systems with 5% supply tolerance. The bq4010Y
monitors for V_PFD = 4.37 V typical for use in 5-V systems with 10% supply tolerance. The bq4010LY monitors for
V_PFD = 2.90 V (typ) for use in 3.3-V systems.
When V_CC falls below the V_PFD threshold, the SRAM automatically write-protects the data. All outputs become
high impedance, and all inputs are treated as don't care. If a valid access is in process at the time of power-fail
detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time t_WPT,
write-protection takes place.
As V_CC falls past V_PFD and approaches V_SO, the control circuitry switches to the internal lithium backup supply,
which provides data retention until valid V_CC is applied.
2
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