BQ4010_14 Datasheet, PDF (10/16 Pages) Texas Instruments – 8 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

bq4010/Y/LY
Not Recommended For New Designs
SLUS116A – MAY 1999 – REVISED JUNE 2007
Address
t_AS
CE
t_WC
t_AW
t_CW
t_WR2
www.ti.com
t_WP
WE
t_DW
t_DH2
D_IN
Data−in Valid
t_WZ
D_OUT
Data Undefined (1)
High−Z
(1) CE or WE must be high during address transition.
(2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not
be applied.
(3) If OE is high, the I/O pins remain in a state of high impedance.
(4) Either t_WR1 or t_WR2 must be met.
(5) Either t_DH1 or t_DH2 must be met.
Figure 9. Write Cycle No. 2 (CE-Controlled) ^{(1)(2)(3)(4)(5)}
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