TM4C129DNCZAD Datasheet, PDF (1903/1967 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCZAD Microcontroller
30.6
30.6.1
Power and Brown-Out
Table 30-13. Power and Brown-Out Levels
Parameter Parameter Parameter Name
No.
Min
Nom
Max
Unit
P1
T_{VDDA_RISE} Analog Supply voltage (V_DDA) rise time
-
P2
T_{VDD_RISE} I/O Supply voltage (V_DD) rise time
-
P3
T_{VDDC_RISEa} Core Supply Voltage (V_DDC) rise time
10
Power-On Reset Threshold (Rising Edge) 1.98
-
-
-
2.35
∞
µs
∞
µs
150
µs
2.72
V
P4
V_POR
Power-On Reset Threshold (Falling Edge) 1.84
2.20
2.56
V
Power-On Reset Hysteresis
0.06
0.15
0.24
V
P5
V_{DDA_POK} V_DDA Power-OK Threshold (Rising Edge)
2.67
2.82
2.97
V
P6
V_{DDA_BOR0} V_DDA Brown-Out Reset Threshold
2.71
2.80
2.89
V
P7
V_{DD_POK}
V_DD Power-OK Threshold (Rising Edge)
V_DD Power-OK Threshold (Falling Edge)
2.65
2.67
2.80
2.76
2.90
2.85
V
V
P8
V_{DD_BOR0} V_DD Brown-Out Reset Threshold
2.77
2.86
2.95
V
P9
V_{DDC_POK}
V_DDC Power-OK Threshold (Rising Edge)
V_DDC Power-OK Threshold (Falling Edge)
0.85
0.71
0.95
0.80
1.10
0.85
V
V
a. The MIN and MAX values are based on an external filter capacitor load within the range of C_LDO. Please refer to “On-Chip
Low Drop-Out (LDO) Regulator” on page 1911 for the C_LDO value.
V_DDA Levels
The V_DDA supply has three monitors:
■ Power-On Reset (POR)
■ Power-OK (POK)
■ Brown Out Reset (BOR)
The POR monitor is used to keep the analog circuitry in reset until the V_DDA supply has reached
the correct range for the analog circuitry to begin operating. The POK monitor is used to keep the
digital circuitry in reset until the V_DDA power supply is at an acceptable operational level. The digital
reset is only released when the Power-On Reset has deasserted and all of the Power-OK monitors
for each of the supplies indicate that power levels are in operational ranges. The BOR monitor is
used to generate a reset to the device or assert an interrupt if the V_DDA supply drops below its
operational range.
Note: V_DDA BOR and V_DD BOR events are a combined BOR to the system logic, such that if either
BOR event occurs, the following bits are affected:
■ BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050.
See page 267.
■ BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control
offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC)
register has been set. See page 269 and page 271.
June 18, 2014
Texas Instruments-Production Data
1903