TM4C129DNCZAD Datasheet, PDF (1559/1967 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCZAD Microcontroller
■ The SR bit of the EMACDMAOPMODE register has been set immediately after being placed in
the RUN state.
■ The data buffer or current descriptor is full before the frame ends for the current transfer.
■ The controller has completed frame reception, but the current receive descriptor is not yet closed.
■ The receive process has been suspended because of a host-owned buffer (RDES0[31]=0) and
a new frame is received.
■ A receive poll demand has been issued.
Receive Frame Processing
The MAC transfers the received frames to the system memory only when the frame passes the
address filter and the frame size is greater than or equal to configurable threshold bytes set for the
RX FIFO, or when the complete frame is written to the RX FIFO in store-and-forward mode.
If the frame fails the address filtering, it is dropped in the MAC block unless the Receive All (RA) bit
is set in the Ethernet MAC Frame Filter (EMACFRAMEFLTR), offset 0x004. If the RA bit is set,
then the MAC passes all received frames. Frames that are shorter than 64 bytes, because of collision
or premature termination, can be removed from the RX FIFO if the DFF bit is clear in the
EMACDMAOPMODE register.
After 64 bytes have been received, the TX/RX Controller requests the DMA block to begin transferring
the frame data to the receive buffer pointed by the current descriptor. The DMA sets the First
Descriptor (RDES0[9]) bit to delimit the frame after the DMA Interface becomes ready to receive a
data transfer (if DMA is not fetching transmit data from the system memory). The descriptors are
released when the OWN (RDES0[31]) bit is reset to 0, either as the data buffer fills up or as the last
segment of the frame is transferred to the receive buffer. If the frame is contained in a single
descriptor, both Last Descriptor (RDES0[8]) and First Descriptor (RDES0[9]) are set.
The DMA fetches the next descriptor, sets the Last Descriptor (RDES0[8]) bit, and releases the
RDES0 status bits in the previous frame descriptor. Then the DMA sets the RI bit of the
EMACDMARIS register. The same process repeats unless the DMA encounters a descriptor flagged
as being owned by the host. If this occurs, the receive process sets the RU bit of the EMACDMARIS
and enters the SUSPEND state. The position in the receive list is retained.
Receive Process Suspend
If a new receive frame arrives while the receive process is in SUSPEND state, the DMA refetches
the current descriptor in the system memory. If the descriptor is now owned by the DMA, the receive
process re-enters the RUN state and starts frame reception. If the descriptor is still owned by the
CPU, by default, the DMA discards the current frame at the top of the RX FIFO and increments the
missed frame counter. If more than one frame is stored in the RX FIFO, the process repeats. The
discarding or flushing of the frame at the top of the RX FIFO can be prevented by disabling flushing
through the DFF bit of the EMACDMAOPMODE register. In such conditions, the receive process
sets the Receive Buffer Unavailable (RU) status and returns to the SUSPEND state.
23.3.3.8
DMA Interrupts
Interrupts can be generated as a result of various transfer events. The current status of interrupts
can be read from the EMACDMARIS register and are enabled to trigger an interrupt through the
programming of the Ethernet MAC DMA Interrupt Mask (EMACDMAIM) register. There are two
groups of transfer event interrupts: Normal and Abnormal. The following lists the two groups:
June 18, 2014
Texas Instruments-Production Data
1559