TM4C129DNCZAD Datasheet, PDF (1444/1967 Pages) Texas Instruments – Tiva Microcontroller

Inter-Integrated Circuit (I²C) Interface
Bit/Field
9
8
7
6
5
4
Name
RXRIS
TXRIS
ARBLOSTRIS
STOPRIS
STARTRIS
NACKRIS
Type
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
Description
Receive FIFO Request Raw Interrupt Status
Value Description
0 No interrupt
1 The trigger level for the RX FIFO has been reached or there is
data in the FIFO and the burst count is zero. Thus, a RX FIFO
request interrupt is pending.
This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.
Transmit Request Raw Interrupt Status
Value Description
0 No interrupt
1 The trigger level for the TX FIFO has been reached and more
data is needed to complete the burst. Thus, a TX FIFO request
interrupt is pending.
This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.
Arbitration Lost Raw Interrupt Status
Value Description
0 No interrupt
1 The Arbitration Lost interrupt is pending.
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR
register.
STOP Detection Raw Interrupt Status
Value Description
0 No interrupt
1 The STOP Detection interrupt is pending.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR
register.
START Detection Raw Interrupt Status
Value Description
0 No interrupt
1 The START Detection interrupt is pending.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR
register.
Address/Data NACK Raw Interrupt Status
Value Description
0 No interrupt
1 The address/data NACK interrupt is pending.
This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR
register.
1444
Texas Instruments-Production Data
June 18, 2014